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Energy Efficient Reconfigurable Architecture for Motion Estimation in Video Coding


  • Computer Science and Engineering, SSN College of Engineering, Chennai - 603110, Tamil Nadu, India


Background/Objectives: Reconfigurable architecture has ability to dynamically allocate the hardware resources during runtime. It can be effectively used in computationally intensive application like media processing. As the motion estimation in video coding consumes large amount of computational time and resources, it can be mapped into reconfigurable architecture to effectively manage the power utilization by dynamic reconfiguration. Methods/Statistical Analysis: A systolic array based reconfigurable architecture for motion estimation which can be configured based on the properties of input video is proposed. A dynamically reconfigurable hardware is designed which can be worked on different search regions based on the level of motion in frames of input video. For the input video, the level of motion among the adjacent frames is determined by motion analyzer. Based on the level of motion between the frames of video, the search window size for block search is selected and this selection will enable the optimum number of processing elements for processing. This dynamic selection of hardware resources based on the search window reduces the power dissipation and computational complexity. Findings: Two search windows have been fixed for analysis 8 × 8 and 7 × 7. For power dissipation analysis, the total logic elements, total registers and fan-out for each design is taken. The performance is analysed by enabling selective number of processing elements for different size of search window. It is observed that power dissipation is high for the search window 8 × 8, because the resource utilization is higher than 7 × 7 search window. Instead of using the same fixed search window for performing block batching, different sized search windows can be used based on the level of motion of the video. After analysis, it is positively found that the proper selection of search window will lead to the optimum utilization in terms of power and resources. Application/Improvements: The context-aware reconfigurable hardware design for highly computationally intensive applications like video processing would be helpful in optimizing the power and resource utilization in hand held devices like smart phones, cam-coders etc.


Motion Estimation, Motion Vector, Power Optimization, Reconfigurable Architecture, Video Coding.

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  • Raha, Jayakumar A, Raghunathan H. Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2008; 99:1–15.
  • Biswas B, Mukherjee R, Chakrabarti I. Efficient Architecture of adaptive rood pattern search technique for fast motion estimation. IEEE transactions on very large scale integration (VLSI) systems for microprocessors and microcontrollers. 2014; 39:200–9.
  • Lu L, McCanny JV, Sezer S. Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding. In Proceedings of IET Computer Digitise Technology. 2010; 349–64.
  • Muralidhar P,.Rama Rao CB, Dwith CYN. Efficient Architecture for Variable Block Size Motion Estimation in H.264/AVC. ACEEE International Journals on Signal and Image Processing. 2014; 5:215–329.
  • Zain-ul-Abdin, Svensson B. Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing. Microprocessors and Microsystems. 2009; 4(33):161–9.
  • Kerr DA. Chrominance Subsampling in Digital Images. In Proceedings of Electronic communications 3(AE). 2014; 107–18.
  • Al-Ani MS, Hammouri TA. Video Compression Algorithm Based on Frame Difference Approaches. International Journal on Soft Computing (IJSC). 2011; 2(4):67–79.
  • Singla N. Motion Detection Based on frame difference method. International Journal of Information and Computation Technology. 2014; 4(15):1559–65.
  • Nithya R, Sarath Chandran KR, Premanand Chandramani V. Run-Time Reconfiguration of Processing Elements through Soft-Core Processor. Third IEEE International Conference on Communication and Signal Processing. IEEE Xplore. 2014 Apr 3-5. p. 813–7. Doi: 10.1109/ICCSP.2014.6949956.


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