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VLSI Design and Implementation of Low Power PBCAM: A Tutorial and Survey

Affiliations

  • Department of Electronics and Communication Engineering, Lovely Professional University, Phagwara - 144411,Punjab, India

Abstract


Background: A CAM is a fully parallel operating device. For high speed data searching functions CAM provides very efficient hardware architecture1. Statistical Analysis: This paper presents novel developments in the recent design of high capacity Content Addressable Memory (CAM) and Pre-computational Based CAM (PB-CAM). A graphical analysis has been shown between PB-CAM using static parameter circuit and proposed parameter circuit for power, delay and power-delay product in 90nm CMOS technology. Findings: There are many techniques made for designing a CAM by taking in mind to get lowpower, low-noise, high-speed, less hardware cost and less data comparisons and with minimum number of transistors and gates. There are, Traditional Dynamic CAM architecture, Ones-Count PB-CAM, Parity function PB-CAM, Remainder function PB-CAM, Block-XOR PB-CAM and Master–Slave Match Line (MSML) design. In this paper we have compared 9T and 7T CAM cell operations. Static parameter circuit is compared with proposed parameter comparison circuit for powerdelay product in 45nm CMOS technology. Applications: CAM function can be used in broader applications, such as data compression, LAN bridges, data comparison, switches, Lookup tables, Asynchronous Transfer Mode (ATM) switches, databases, communication devices, communication networks, tag directories and high speed Ethernet etc.

Keywords

Block-XOR, CAM, Master-Slave, Match-Line, Ones-Count, PB-CAM, Parity, Remainder.

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References


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