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A Study of Traditional and Surrounding Gate MOSFET using TCAD Simulations


  • ECE, Amity School of Engineering and Technology, Gurgaon, Haryana, India


In this paper, Traditional and surrounding gate MOSFET are simulated using TCAD Silvaco and report the effect of multigate transistor. As the channel length of transistors is scaling down, a traditional MOSFET suffers from short channel effects and degrade the device performance. The different parameter such as threshold voltage, area, subthreshold slope, channel length modulation and leakage current are extracted for traditional and surrounding gate MOSFET. The parameters obtained from surrounding gate MOSFET is compared with a traditional MOSFET of the same dimension. The Results show that better performance was obtained for surrounding gate MOSFET. Its current drive capability is more as compared to traditional MOSFET .However, benefits of achieving superior performance with surrounding gate MOSFET reduces in terms of poor RF performance. Hence, this paper concludes that surrounding gate MOSFET have huge potential to be a promising contender to the traditional MOSFETs for making of future generation low-power high speed devices which could minimize the occupied area.


Channel Length Modulation, Leakage Current, Subthreshold Slope, Surrounding Gate MOSFET, Threshold Voltage.

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  • Takato H, Sunouchi K, Okabe N, Nitayama A, Hieda K, Horiguchi F, Masuoka F. Impact of Surrounding Gate Transistor (SGT) for Ultra-High-Density LSI’s. IEEE Transactions on Electron Devices. 1991 Mar; 38(3).
  • Subrahmanyam B, Jagadesh Kumar M. Department of Electrical Engineering, Indian Institute of Technology.Recessed source concept in nanoscale vertical surrounding gate (VSG) MOSFETs for controlling short-channel effects, New Delhi 110 016 India, Physica E. 2009; 41:671–6
  • Gupta N, Raghav AK, Kushwaha AK. A study on multi material gate all around SOI MOSFET. International Journal of Technological Exploration and Learning. 2014 Jun; 3(3).
  • Solankia T, Parmar N. A Review paper: A Comprehensive study of junctionless transistor. National Conference on Recent Trends in Engineering and Technology, B.V.M.Engineering College, V.V. Nagar, Gujarat, India. 2011 May13-14.
  • Chen C-Y, Lin J-T, Chiang M-H. Comparative Study of Process Variations in Junctionless and Traditional DoubleGate MOSFETs, IEEE. 2013.
  • Lakshmi B, Srinivasan R. Investigation of ft and nonquasistatic delay in traditional and junctionless multigate transistors using TCAD simulation. ARPN Journal of Engineering and Applied Sciences. 2012 Jul; 7(7).
  • Kim SY et al. Design and Analysis of Sub-10 nm Junctionless Fin-Shaped Field-Effect Transistors. Journal of Semiconductor Technology and Science. 2014 Oct; 14(5).
  • SILVACO International, ATLAS User ’s Manual, 2012 Apr.
  • Gupta SK, Pathak GG, Das D, Sharma C. Double Gate MOSFET and its Application for Efficient Digital Circuits. International Conference on Electronics Computer Technology, IEEE. 2011. Doi: 10.1109/ ICECTECH.2011.5941650.
  • Gupta N, Patel JKB, Raghav AK. A study on roadmap for future multi gate SOI mosfet. International Journal of Engineering Research. 2015 Jan; 3(1):1–7.
  • The International Technology Roadmap for Semiconductors, 2007.
  • Gupta N, Patel JKB, Raghav AK. A Study of Conventional and Junctionless MOSFET Using TCAD Simulations.International Conference on Advanced Computing and Communication Technologies, IEEE. 2015. Doi: 10.1109/ ACCT.2015.51.
  • Fashtami TN, Seyed Ali SZ. Performance Investigation of Gate-All-Around Nanowire FETs for Logic Applications.Indian Journal of Science and Technology. 2015 Feb; 8(3):231–6.
  • Verma JHK, Haldar S, Gupta RS, Gupta M. Modelling and simulation of subthreshold behaviour of cylindrical surrounding double gate MOSFET for enhanced electrostatic integrity. Super lattices and Microstructures. 2015 Sep; 354–64.
  • Yu F, Deng W, Huang J, Ma X, Chen S. An Explicit PhysicsBased I –V Model for Surrounding-Gate Polysilicon Transistors. IEEE Transactions on Electron Devices. 2016 Mar; 63(3):1059–65.
  • Charles Pravin J, Nirmal D, Prajoon P, Ajayan J.Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications. Physica E. 2016 Apr; 83:95–100.
  • Xiao Y, Zhang B, Lou H, Zhang L, Lin X. A Compact Model of Subthreshold Current with Source/Drain Depletion effect for the Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs. IEEE Transactions on Electron Devices. 2016 May; 63(5):2176–81.


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