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Design of PLL based Frequency Synthesizer using Harmonic Extraction Techniques

Affiliations

  • SRM University, Kattankulathur, Chennai – 603203, Tamil Nadu, India

Abstract


Objectives: This paper introduces a design of PLL based Frequency Synthesizer using Harmonic Extraction Technique. Different parameters of PLL and Frequency Synthesizer are analyzed. Methods: The Harmonic Extraction technique includes VCO with common gate amplifier, cascode amplifier and Differential output Buffer. The LC tank circuit used in this paper is a current mirror VCO. In order to extract the harmonics, Band pass filter is used. After that dual loop PLL is introduced which consists of proportional path and integral path. Furthermore Phase and Frequency Detector (PFD) is implemented using Gate Diffusion input (GDI) method. The proposed design is implemented using 90nm Cadence Virtuoso Analog Design Environment tool. Findings: As a result of using this technique, VCO achieves tuning range of 23.17% and phase noise of -85dBc/Hz @1MHz and -93dBc/Hz@10MHz with a small power dissipation of 50uW and Frequency Synthesizer achieves power dissipation of 4.8mW. Improvements/Applications: The performance analysis has shown that the designed Frequency Synthesizer has better tuning range, low power and low Phase noise which makes it suitable to operate in high frequency applications.

Keywords

Band Pass Filter (BPF), Dual Loop PLL, Frequency Synthesizer, GDI, Harmonic Extraction, PFD, PLL, VCO.

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References


  • Copani T. A 0.13- m CMOS local oscillator for 60-GHz applications based on push-push characteristic of capacitive degeneration, IEEE Radio Frequency Integrated Circuits Symposium. 2010 May. p. 153–6.
  • Chao Y. A 0.6-V 14.1-mW 96.8 GHz-to-108.5 GHz transformer-based PLL with embedded phase shifter in 65nmCMOS. IEEE Radio Frequency Integrated Circuits Symposium. 2014 Jun. p. 93–96.
  • Liu RC. A 63 GHz VCO using a standard 0.25 um CMOS process. Solid-State Circuits Conference. Digest of Technical Papers. ISSCC IEEE International. 2004 Feb; 1:446–7.
  • Sadhu B, Ferriss M, Garcia AV. A 52 GHz frequency synthesizer featuring a harmonic extraction technique that preserves VCO Performance. IEEE Journal of Solid-state Circuits. 2015 May; 50(5):1214–23.
  • Sadhu B. A linearized low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE Journal of Solid-State Circuits. 2013 May; 48(5):1138–11550.
  • Ferriss M. An integral path self-calibration scheme for a dual loop PLL. IEEE Journal of Solid-State Circuits. 2013 Apr; 48(4):996–1008.

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