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Design and Implementation of Floating Point Unit using 15 nm FIFET

Affiliations

  • Department of Micro and Nano Electronics, VIT University, Vellore - 632014, Tamil Nadu, India

Abstract


Objectives: To design a 32-bit IEEE 754 floating point standard based MAC unit using 15 nm FinFET. In MAC unit given data is multiplied and accumulated in a register which are processed separately as exponent and mantissa but there are some issues regarding area power and timing, compromising these constraints is bit difficult. Methods: The proposed architecture of floating point MAC unit is majorly divided into multiplier and accumulator components in these blocks the sub blocks are designed with Han-Carlson adder, Vedic multiplier, barrel shifter and comparator. Findings: The previous work was done in Hardware Description Language (HDL) in which the design will map to CMOS or pass transistor components after synthesis so designing of each component with transistors of 15 nm FINFET becomes vital. The entire design is carried out in cadence virtuoso and layout editor for timing, area and power. The performance can be increased if the computations are performed with less number of transistors. However, the decimal operations have been limited due to the increase in cost and complexity of hardware components. DFP arithmetic is used for the complex computations, it consumes more power because of the area it occupied when implemented in hardware. Improvements/Applications: Because of battery driven property low power with high performance are given major importance.

Keywords

Barrel Shifter and Comparator, Han-Carlson Adder, Leading One Detector, MAC Unit (Multiplication and Accumulation Unit), Vedic Multiplier.

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References


  • Krishna VV, Kumar SN. High speed, power and area efficient algorithms for ALU using Vedic mathematics. International Journal of Scientific and Research Publications. 2012 Jul; 2(7):1–6.
  • Binary adder architectures for cell-based VLSI and their synthesis. 2014. Available from: http://www.slideshare.net/prasannaincito/binary-adder-architectures-for-cellbased-vlsi-and-their-synthesis
  • Nesam JJ, Sathasivam S. An efficient single precision floating point multiplier architecture based on classical recoding algorithm. Indian Journal of Science and Technology. 2016 Feb; 9(5):1–7.
  • Begum JT, Naidu SH, Vaishnavi N, Sakana G, Prabhakaran N. Design and Implementation of reconfigurable ALU for signal processing applications. Indian Journal of Science and Technology. 2016 Jan; 9(2):1–6.
  • Barrel shifter or multiply/divide IC structure. 1995. Available from: http://patents.com/us-5465222.html
  • Han T, Carlson DA. Fast area-efficient VLSI adders. 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH); 1987 May. p. 49–56.
  • Brent RP, Kung HT. A regular layout for parallel adders. IEEE Transaction on Computer. 1982 Mar; 31(3):260–4.
  • Kogge PM, Stone HS. A parallel algorithm for the efficient solution of a general class of recurrence equations. IEEE Transactions on Computers. 1973 Aug; C-22(8):786–93.
  • Mishra P, Jha NK. Low-power Fin FET circuit synthesis using surface orientation optimization. Proceedings of the Conference on Design, Automation and Test in European Design and Automation Association; 2010 Mar. p. 311–4.
  • Muttreja A, Agarwal N, Jha NK. CMOS logic design with independent-gate Fin FETs. 25th International Conference on Computer Design, 2007 ICCD; 2007 Oct. p. 560–7.

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