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An Efficient Technique to Reduce Average and Peak Power in Scan Based BIST


  • School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, India


Objectives: A low-transition Test Pattern Generator (TPG) known as Bit Swapping LFSR (BS-LFSR) which generates the test vectors with low transitions. This will increase the correlation and results in one transition between the consecutive test patterns. Methods: The BS-LFSR comprises of an external XOR type LFSR along with multiplexer. The bit swapped test patterns alone is not enough to reduce the average and peak power. The Weighted Transition Metric (WTM) is calculated after shifting of test patterns into the scan cells. Based on WTM values for each test pattern, scan cells are reordered to reduce the test power. Findings: The various CUTs are chosen from ISCAS 89 standard benchmark circuits. The CUTs are synthesized using RTL Compiler tool from Cadence and the scan chain inserted Gate Level Netlist are obtained for each CUT respectively. Improvements: Experimental results show that power reduction is attained by employing the technique.


BIST, LFSR, Scan Chain Reordering, Test Pattern Generator.

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