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Clock Scheme for FPGA Implementation of Globally Asynchronous Locally Synchronous Circuits
Objective: In this paper clock scheme for FPGA implementation of globally asynchronous locally synchronous circuits to achieve low power dissipation by reducing switching power consumption in a circuit is proposed. Method: Clock scheme for globally asynchronous locally synchronous (GALS) using clock divider and decoder module is evaluated. Clock divider and decoder module mainly divides a global clock into low switching rate control signals that simplifies in circuit clock management modules and reduce global clock rate. Findings: Asynchronous or clockless designs are considered as an alternative to conventional synchronous digital system design. The major advantages of asynchronous are low power consumption, better modularity, higher robustness and higher speed. Traditional Quasi-Delay-Insensitive (QDI) circuits are nearly impossible to be mapped onto commercial FPGAs. The correctness of a circuit using a bundled-data scheme depends on the assumption that the delay of each block (including logic and routing) is predictable and designers can use a delay-matching block to satisfy timing constraint. Clock divider and decoder modules does not incorporates delay matching block. Global clock is finely partition to the low rate control signals that results in low power dissipation with less complex circuitry and most importantly facilitates FPGA implementation.
Clock Scheme, FPGA, GALS, Low Power, Switching Power
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