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Optimizing Power in Sequential Circuits by Reducing Leakage Current using Enhanced Multi Threshold CMOS

Affiliations

  • Department of ECE, JNTUK, Kakinada – 533003, Andhra Pradesh, India
  • ECE, T.R.R College of Engineering, Hyderabad - 502301,Telangana, India

Abstract


Technical thirst of man is in exponential rise and posing critical challenges in using this technology. This is much evident in the design of VLSI circuits. Sequential circuit designing demands lesser energy consumption, smartness and increased functional density. In this domain, every development in the recent past has energy as the focal point. MTCMOS exactly serves the purpose of reduced power consumption in digital circuits. This technique provides lower leakage current and offers enhanced speed. It uses low threshold voltage devices for low leakage and high threshold voltage components as sleep transistors. These sleep transistors are good enough to isolate the logic modules from the supply, ground in order to reduce the leakage current. Care is ensured particularly in the mode transition and also the least possible time for turn ON state in a circuit, as these are the primary concerns for power consumption and thereby for the performance degradation of integrated circuits. In this paper, a successful attempt was made in enhancing the advantage of employing MTCMOS technique towards lesser power consumption in sequential circuit designing.

Keywords

Leakage Current and Sequential Circuit, MTCMOS, Power or Energy Consumption.

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