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An Optimized Successive Approximation Register used in ADC for Wireless Sensor Nodes

Affiliations

  • Sardar Patel Institute of Technology, Andheri, Mumbai – 40058, Mumbai University Research Center, India
  • Department of Electronics and Telcommunication Engineering, St. Francis Institute of Technology, Borivali (W),Mumbai – 400103, India

Abstract


SAR plays an important role in ADC used in WSN. To finding out comparator resolving time and its relation to the DAC settling time. This paper describes a mathematical analysis of resolving time of a synchronous and asynchronous type of a Successive Approximation Register (SAR) ADC. We have derived the relation ratio of asynchronous and synchronous resolving time for a number of bits. The mathematical analysis verified using Scilab 5.2.2. The comparator resolving and DAC settling timing constraints have the tradeoff between power and speed. The maximum resolving time satisfies both the first order and second order derivative test and shows the reduction of two times resolving time between synchronous and asynchronous. As the number of resolution bits increases, the conversion time of asynchronous SAR decreases compared to synchronous. This can lead to saving the power as well as improves the speed. The SAR architecture is suitable for a low power, and high-speed sensor node data acquisition used in WSNs.

Keywords

Analog to Digital Converter (ADC), Asynchronous, Conversion time, Digital-to-Analog Converter (DAC), Resolving time, Settling time, Synchronous, Successive Approximation Register (SAR), Wireless Sensor Node (WSN).

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