Total views : 215

Design of Combined Radix-2, Radix- 4 and Radix-8 based Single Path Delay Feedback (SDF) FFT


  • Department of ECE, St. Peter’s University Chennai - 600054 , Tamil Nadu, India
  • Department of ECE, Sathyabama University, Chennai - 600119, Tamil Nadu, India


Objectives: FFT algorithm is used for enhancing the performance of DFT.In the previous years, various types of FFT algorithms have been introduced. Particularly, the pipeline algorithms have been reputed as proper algorithms for processing high-speed data. Some pipeline FFT algorithms like split radix, radix-2 and the mixed radix have been developed. Methods: In the existing method of Radix-2 SDF FFT has more hardware utilization and also computational stages are increased. Findings: To conquer this problem, we developed a combined radix-2, 4 & 8 butterfly elements based Single path Delay Feedback (SDF) fast fourier transform method for reducing the computational stages in this paper. The developed method has the identical number of multipliers and the smaller number of stages and butterfly elements than the existing radix-2 FFT. Improvements: This architecture offers 62.47% reduction in LUTs, 58.78% reduction in slices, and 37.85% reduction in delay and 30.86% reduction in power consumption than the existing method.


Discrete Fourier Transform (DFT), Fast Fourier Transform (FFT), Look Up Tables (LUTs), Single path Delay Feedback (SDF).

Full Text:

 |  (PDF views: 294)


  • Wang L, Zhou X, Sobelman GE, Liu R. Generic mixed-radix FFT pruning. IEEE Signal Processing Letters. 2012; 19(3):167–70.
  • Bouguezel S, Ahmad MO, Swamy MS. A new radix 2 or 8 FFT for length -q× 2m DFTs. IEEE Transactions on Circuits and Systems. 2014; 51(9):1723–32.
  • Jia L, Gao Y, Tenhunen H. Efficient implementation of radix-8 FFT algorithm. IEEE Pacific Rim Conference on Communications, Computers and Signal Processing; 1999.p. 468–71.
  • Kumar A, Mishra M, Verma RK. Design a parallel pipeline Radix-4 FFT Architecture. International Journal of Scientific Research and Management. 2014; 2(10).
  • Jayaram K, Arun C. Survey report for Radix-2, 4 and 8 FFT algorithms. International Journal of Innovative Research in Science, Engineering and Technology. 2015; 4(7).
  • Mookherjee S, DeBrunner L, DeBrunner, V. A low power radix-2 FFT algorithm for FPGA. IEEE Conference on Signals, Systems and Computers; 2015. p. 447–51.
  • Mookherjee S, DeBrunner L, DeBrunner V. A high-throughput and low-power radix-4 FFT architecture. IEEE Conference on Signals, Systems and Computers; 2014. p. 1266–70.
  • Cherkauer BS, Friedman EG. A hybrid radix-4 & 8 low power, high speed multiplier architecture for wide bit widths. IEEE International Symposium on Circuits and Systems. 1996; 4:53–6.
  • Malathy K, Rabi BJ. A novel VLSI based Radix-2 Single path Delay Commutator (R2SDC) FFT architecture design.Indian Journal of Science and Technology. 2016; 9(11).


  • There are currently no refbacks.

Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.