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Impact of Process Variations on Open Circuit Voltage Gain of CMOS Inverting Amplifiers

Affiliations

  • Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi - 835215, Jharkhand, India

Abstract


Objectives: The impact of process variations on the open circuit voltage gain of CMOS inverting amplifiers is investigated and appropriate aspect ratios are calculated so as to minimize the effect of threshold voltage modulation in short channel devices. Methods/Analysis: A diode connected MOS voltage divider is used for biasing the amplifiers. These dividers are less bulky as compared to their resistive counterparts, save chip area and provide better reliability when subjected to variations. Findings: The sensitivity parameters for the voltage gain are modeled and their dependences are studied. All simulation results have been performed using CADENCE Virtuoso Analog Design Environment @ 45-nm technology node. Application: Push-pull inverting amplifiers are used in CMOS Transimpedance Amplifier forlow noise, high gain and large dynamic range. Transimpedance amplifiers find numerous applications inthe field of optical communications.

Keywords

Aspect Ratio, Gain, Inverting, MOS Divider, Saturation, Sensitivity, Variability.

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References


  • Liu Y, Yuan J. CMOS RF power amplifier variability and reliability resilient biasing design and analysis. IEEE Transactions on Electron Devices. 2011; 58(2):540–46.
  • Mukadam MY, Filho OCG, Kramer N, Zhang X, Apsel AB. Low-power, minimally invasive process compensation technique for sub-micron CMOS amplifiers. IEEE Transactions on VLSI Systems. 2014; 22(1):1–12.
  • Pappu NAM, Zhang X, Harrison AV, Apsel AB. Process-invariant current source design: Methodology and example. IEEE Journal of Solid-State Circuits. 2007; 42(10):2293–302.
  • Gómez D, Sroka M, González Jiménez JL. Process and temperature compensation for RF low-noise amplifiers and mixers. IEEE Transactions on Circuits and Systems-I: Regular Papers. 2011; 57(6):1204–11.
  • Siddharth S, Srikanth M, Shantanu J, Sakthivel R. Efficient VCO using FinFET. Indian Journal of Science and Technology. 2015 Jan; 8(S2):262–70 .
  • Chen J, Ker M. The impact of gate-oxide breakdown on common-source amplifiers with diode-connected active load in low-voltage CMOS processes. IEEE Transactions on Electron Devices. 2007; 54(11):2860–70.
  • Li Y, Hwang CH, Li T, Han MH. Process-variation effect, metal-gate work-function fluctuation, and random-dopant fluctuation in emerging CMOS technologies. IEEE Transactions on Electron Devices. 2007; 57(2):437–47.
  • Shekhar V, Kaur MG. Comparative analysis of process variation on single bit domino full adder with single bit static full adder. Indian Journal of Science and Technology. 2015 Aug; 8(17):1–7.
  • Baker RJ. CMOS circuit design, layout, and simulation, 3rd (edn.), Wiley-IEEE Press: US; 2010 Aug.
  • Toyabe T, Asai S. Analytical models of threshold voltage and breakdown voltage of short-channel MOSFET's derived from two-dimensional analysis. IEEE Transactions on Electron Devices. 1979; 26(4):453–61.
  • Allen PE, Holberg DR. CMOS analog circuit design, 3rd (edn.), Oxford University Press: New York; 2011. p. 784.
  • Alioto M, Consoli E, Palumbo G. Variations in nanometer CMOS flip-flops: Part I-impact of process variations on timing. IEEE Transactions on Circuits and Systems I: Regular Papers. 2015; 62(8):2035–43.

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