Total views : 176
Robust Design of Differential Amplifier with Diode-connected Voltage Reference
Objectives: The impact of process, voltage and temperature (PVT) variations on the voltage gain of a CMOS differential amplifier is investigated. Methods and analysis: Appropriate biasing is provided using diode-connected MOS voltage dividers. These dividers are less bulky as compared to their resistive counterparts, save chip area and provide better performance when subjected to variations. In addition, the transistors are sized suitably to minimize the effect of threshold voltage modulation in short-channel devices. Findings: The sensitivity parameters for the voltage gain are modeled and their dependences are studied. All simulation results have been performed using Virtuoso Analog Design Environment of Cadence @ 45-nm technology node. Application/ Improvement: Diode-connected MOS voltage dividers are used to bias the amplifier which provide immunity against PVT variations and hence improve system performance.
Aspect Ratio, Differential, Gain, MOS Divider, Saturation, Sensitivity, Variability.
- Liu S, Yuan Y. MOS rf power amplifier variability and reliability resilient biasing design and analysis. IEEE Transaction on Electron Devices. 2011; 58(2):540–6.
- Mukadam MY, Oscar C, Filho F, Kramer N, Zhang X, Psel AB. Low-power, minimally invasive process compensation technique for sub-micron CMOS amplifiers. IEEE Transaction on Very Large Scale Integration System. 2014; 22(1):1–12.
- Gómez D, Sroka M, Jiménez JLJ. Process temperature compensation for RF low-noise amplifiers and mixers. IEEE Transaction on Circuits and System I: Regular Papers. 2007; 57(6):1204–11.
- Siddharth S, Srikanth M, Shantanu J, Sakthivel R. Efficient VCO using FinFET. Indian Journal of Science and Technology. 2015 Jan; 8(2):262–70.
- Count L. Analog and mixed-signal innovation: The process-circuit system- application interaction. Proceeding of IEEE International Solid-State Circuits Conference on Wilmington; 2007.
- Annema AJ, Nauta B, van Langevelde B , Tuinhout H. Analog circuits in ultra-deep-submicron CMOS. IEEE Journal of Solid-State Circuits. 2005; 40(1):132–43.
- Sanapala K, Sakthivel R. Low power realization of subthreshold digital logic circuits using body bias technique. Indian Journal of Science and Technology. 2016 Feb; 9(5):1–5.
- Li Y, Hwang CH, Li TY, Han MH. Process-variation effect, metal-gate work-function fluctuation, and random-dopant fluctuation in emerging CMOS technologies. IEEE Transaction on Electron Devices. 2010; 57(2):437–7.
- Shekhar V, Kaur MG. Comparative analysis of process variation on single bit domino full adder with single bit static full adder. Indian Journal of Science and Technology. 2015 Aug; 8(17):1–7.
- Baker RJ. CMOS circuit design, layout, and simulation, 3rd (edn.), Wiley-IEEE Press:US; 2010.
- Toyabe T, Asai S. Analytical models of threshold voltage and breakdown voltage of short-channel MOSFET's derived from two-dimensional analysis. IEEE Transaction on Electron Devices. 1979; 26(4):453–61.
- Allen PE, Holberg DR. CMOS analog circuit design, 3rd (edn.), Oxford University Press: New York; 2012.
- Alioto M, Consoli E, Palumbo G. Variations in nanometer CMOS flip-flops: Part I—impact of process variations on timing. IEEE Transaction on Circuits Systems I: Regular Papers. 2015; 62(8):2035–43.
- Kanda K, Kawaguchi HN, Sakurai T. Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs. IEEE Journal of Solid-State Circuits. 2001; 36(10):1559–64.
- There are currently no refbacks.
This work is licensed under a Creative Commons Attribution 3.0 License.