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A Novel Paradigm to Eliminate Timing Violations using AHL


  • Department of ECE, Kumaraguru College of Technology, Coimbatore – 641049, Tamil Nadu, India
  • Karpagam Academy of Higher Education, Coimbatore - 641021, Tamil Nadu, India
  • Department of ECE, Karpagam Academy of Higher Education, Coimbatore - 641021, Tamil Nadu, India


Objectives: This Paper presents a novel low power design approach for multipliers to eliminate timing violations. There are two major issues which are concentrated in this paper are positive bias temperature instability and negative bias temperature instability. Both the things affect the speed of transistor and leads to timing violations, which intern leads to the failure of an entire system. Methods: In this work, bypassing multiplier is used with adaptive hold logic. The implementation is done in 180 nm deep submicron CMOS technology. Findings: power consumption and error rate is studied after employing the AHL. Improvements: The experimental result shows that the performance of multipliers with AHL improved 72.8% when compared to existing methods and consumes less power.


AHL, Bypass Multipliers, Low Power Design, Instability, Timing Violations.

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