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Design of Low Power 6T-SRAM Cell and Analysis for High Speed Application

Affiliations

  • Department of Electronics and Instrumentation Engineering, M. S. Ramaiah Institute of Technology, Vidya Soudha,MSR Nagar, MSRIT Post, Bangalore, India
  • Department of Electronics and Communication Engineering, Channabasaveshwara Institute of Technology, N.H. 206, B.H. Road, Gubbi, Tumkur –572216 (Near Bangalore), Karnataka, India

Abstract


Static Random Access Memory (SRAM) is one of the core components in the digital world. Generally, it consumes enormous amount of power and die area. Thereby extensive research in SRAM is in progress related power dissipation, memory chip area and supply voltage requirement. In this paper SRAM analysis in terms of Static Noise Margin, Data Retention Voltage, Read Margin (RM) and Write Margin (WM) for low power application is considered. Static Noise Margin (SNM) is one of the most essential parameter for memory design because it affects both read and write margin. SNM is related to the threshold voltages of the Negative Metal Oxide Semiconductor (NMOS) and Positive Metal-Oxide Semiconductor (PMOS) devices of the SRAM cell. High Read and Write Noise Margin are also significant challenges in the design of SRAM. Data Retention Voltage (DRV) is calculated for 6T-SRAM cell for high-speed application. Different types of curve are taken straightforwardly to analyses the 6t-SRAM by varying the size of the transistor. Performance analysis is estimated in 6T-SRAM designed and implemented in 90nm technology.

Keywords

Data Retention Voltage, Noise Margin, Read Margin, SRAM, 6T-SRAM, Virtuoso, Write Margin.

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References


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