Total views : 125
Study and Designing of Fourth Order BEC Circuit for Flash Analog to Digital Converter using MUX based Encoder
Objectives: To design and study a fourth order Bubble error correction circuit for a Flash Analog to Digital Converter by making use of a Multiplexer based encoder. Methods/Statistical Analysis: A Thermometer to binary encoder acts as a vital element in the functioning of flash ADCs. Output of flash ADCs is in thermometer code. Ideally, Thermometer code shows single transition but in case of clock jitter and device mismatch, multiple transitions take place introducing bubbles in the code. This error leads to inaccurate encoding process. A Bubble error correction circuit has been proposed that eliminates bubble error upto fourth order as compared to existing circuit that eliminated error only upto third order. Simulation shows the transistor requirement of existing and proposed circuit is same thus making present circuit more efficient and acceptable. Findings: The Number of transistors required in different types of encoders can be understood through the tables. Although ROM based encoder along with BEC circuit requires 714 transistors which is less than other circuits. But since the conversion speed of ROM based encoder is relatively slow and because of constant static current which is used for presetting the encoder, the power consumption goes high and so ROM based encoder is avoided. Wallace tree requires lesser transistors but is unsuitable for the high speed of operations. Fat tree encoder along with BEC circuit requires 832 transistors. It has slightly less transistor requirement than proposed circuit but its difficult layout prevents us from using it. All the three encoder types mentioned in the table namely ROM based, Wallace tree and fat tree encoders are capable to remove bubble error only upto 3rd order. In case designing is done to remove higher order bubble error considers it to be fourth then definitely the transistor count will increase. However our proposed BEC circuit with MUX based encoder eliminates bubble error upto fourth order. It can be seen from the table ,the transistor count in new BEC circuit for removing fourth order error nearly matches the transistor count for removal of third order error by remaining encoders. Thus existing circuits and proposed circuit will have much difference in their efficiency of operation. Lesser number of transistor requirements makes our circuit more acceptable and efficient. Application/Improvements: Varying the (W/L) ratio may contribute in bringing changes in the delay and the average power dissipation making the circuit more efficient. CMOS inverter is susceptible to the process and the temperature variation. Temp variation would make the threshold voltage change so we may use another design whose comparator uses a self tuned inverter.
Flash ADC, MUX based Encoder, 4th Order Bubble Error Correction Circuit, TIQ.
- Daly DC, Chandrakasan AP. A 6-bit, 0.2 V to 0.9 V highly digital flash ADC with comparator redundancy, solid-state circuits. IEEE Journal. 2009 Nov; 44(11):3030-38.
- Deguchi K, Suwa N, Ito M, Kumamoto T, Miki T. A 6-bit 3.5- GS/s 0.9-V 98-mW flash ADC in 90-nm CMOS, SolidState Circuits. IEEE Journal. 2008 Oct; 43(10):2303-10.
- andner C, Clara M, Santner A, Hartig T, Kuttner F. A 6-bit 1.2-GS/s low-power flash-ADC in O.13-and mum digital CMOS, Solid-State Circuits. IEEE Journal. 2005 Jul; 40(7):1499-505.
- Plassche R J V D. CMOS integrated analog-to-digital and digital-to analog converters. 2nd (edn)., Springer Science+Business Media: New York, 2003, pp.588.
- Piyush K. Low-power heterogeneous encoder based 4-bit flash ADC using TIQ. International Journal of Electrical and Electronics Research. 2015; 3(2):662–9.
- Agrawal N, Paily R. An improved ROM architecture for bubble error suppression in high speed flash ADCs. Annual IEEE Conference; Aalborg. 2008. p. 1–5. Crossref
- Sall E, Vesterbacka M, Anderson KO. A study of digital decoders in flash analog-to-digital converters. International Symposium Proceedings of the 2004 Circuits and Systems; 2004. p. I-129–32. Crossref
- Razavi B. Principles of Data Conversion System Design. 1st ed. New York: IEEE Press; 1995.
- Chunn A, Sarin RK. Comparison of thermometer to binary encoders for flash ADCs. Annual IEEE India Conference on INDICON; Mumbai. 2013. p. 1–4. Crossref
- Jen CY, Hung OH, Da LB. A novel bubble tolerant thermometerto-binary encoder for flash A/D converter. IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test; 2005. p. 315–8.
- Daegyu L, Jincheol Y, Kyusun C, Ghaznavi J. Fat tree encoder design for ultra-high speed flash A/D converters. The 45th Midwest Symposium on Circuits and Systems; 2002. p. II-87-90.
- Sall E, Vesterbacka M. Comparison of two thermometer-tobinary decoders for high-performance flash ADCs. IEEE 23rd Conference on NORCHIP; 2005. p. 253–6. Crossref
- Sail E, Vesterbacka M. A multiplexer based decoder for flash analog-to-digital converters. IEEE 10th Conference TENCON Region; 2004. p. 250–3. Crossref
- Hieu BV, Beak S, choi S, seon J, Jeong TD. Thermometer to binary encoder with Bubble Error Correction (BEC) circuit for Flash Analog to Digital Converter (FADC). 3 rd International Conference Communications and Electronics (ICCE); Aug201011-13. P. 102–6.
- There are currently no refbacks.
This work is licensed under a Creative Commons Attribution 3.0 License.