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Design and Performance Analysis of RAM_WR_ Control Module using Xilinx ISE 14.2


  • Department of Computer Science & Engineering, Chitkara University Institute of Engineering & Technology, Chitkara University, India
  • Department of Electronics & Communication Engineering, Chitkara University Institute of Engineering & Technology, Chitkara University, India
  • Techno planet labs Pvt Ltd, Faridabad - 121003, Haryana, India


In the following work RAM_Write_Control module has been designed and its performance has been analyzed in terms of utilization of power and energy in order to make it energy and power efficient. The main idea behind this unit is to control the data write operation to the core which is used for saving the raw data in impedance measurement module of Electrical Impedance Tomography (EIT) system, KHU Mark 2.5. The performance of the unit is analyzed using 14.2 version of Xilinx software at Virtex-5 FPGA chip. The total power consumption of 3 logic families HSTL (High Speed Transceiver Logic), LVCMOS (Low Voltage Metal Oxide Semiconductor) and LVTTL (Low Voltage Transistor-Transistor Logic) at different I/O Standards have been compared in order to excrete out the most energy efficient logic family. Frequency scaling technique has also been applied by varying the frequencies at a scale of 100 Hz i.e., from 400MHz to 500 MHz to 600 MHz to 700 MHz in a way to find out the most power efficient frequency. It has been observed minimum power consumption occurs in case if we use LVCOMS15 I/O standard of LVCMOS logic family in comparison to other IO standards of other 2 logic families. And this maximum power savage occurs at a lowest frequency of 400 MHz.


Energy Efficiency, EIT RAM, FPGA, System, WRITE CONTROL, Xilinx.

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