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FPGA Implementation of Convolution for Data Hiding Application
Convolution plays a major role in various DSP applications. Convolution can be achieved by means of multiplication and addition operations. The multiplier is the key element which influences the power consumption, speed and area of the Convolution system. The traditional multipliers such as Array multiplier, Wallace tree multiplier, Booth multiplier suffer with high power consumption and more delay. The multiplier based on Vedic Mathematics exhibits low power consumption and less delay when compared to traditional multipliers. Hence, Vedic multiplier and Vedic divider are proposed to use in the design of Convolution and Deconvolution respectively. The design and implementation of Convolution and Deconvolution using Vedic Architecture on FPGA are performed and the results indicate that it gives improved performance with regard to power and delay. This proposed Convolution based on Vedic multiplier is explored for data hiding applications.
Convolution, Data Hiding, Deconvolution, FPGA, Vedic Multiplier.
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