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Low Complexity Digit Serial Multiplier for Finite Field using Redundant Basis


  • Department of ECE, Shri Vishnu Engineering College for Women (Autonomous), Bhimavaram −534202, Andhra Pradesh, India


Cryptography has been increasingly used due to its rapid trends. In recent days, it has been used mostly in communication and in financial transactions through automated machines or internet. The applications of cryptography and coding theory require finite field operations and are realized based on the finite field computations. In this paper efficient digit-serial multiplier over finite field is implemented and is obtained by using Redundant Basis (RB), intend to present highthroughput multiplier. Area and power are the two factors which obtain less when compared to the previous multipliers. The digit-serial multiplier for 32-bit is implemented using Verilog HDL and synthesized to know its better performance in terms of area and power compared to previous multipliers.


Cryptography, Digit-Serial, Finite FIELD, Redundant Basis.

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  • Niederreter H, Lidl R. Introduction to Finite Feilda and their Application, Cambridge University Press, 1986.
  • Zhi-Hong Mao, Xie J. High Throughput Finite Field Multipliers using Redundant Basis for FPGA and ASIC Implementation, IEEE Transc. Circt. Syst. I. 2015 Jan; 62(1):110−19.
  • David I, Thomas C. Computation with Finite Fields, Information and Control. 1963; 6:79−98.
  • Chiou-Yng Lee, Chun-Sheng Yang. Low-Complexity Digit-Serial and Scalable SPB/GPB Multipliers Over Large Binary Extension Fields using (b,2)-Way Karatsuba Decomposition, IEEE Trans. Circ. And Syst.- I. 2014; 61(11):3115−24.
  • Jiafeng Xie. Low-Complexity Multiplier for GF (2m) based on All-One Polynomials, IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013; 21(1):168−73.
  • Huapeng Wu. Finite Field Multiplier using Redundant Representation, IEEE Trans. Comp. 2001; 51(11):1306−16.
  • Chiou-Yng Lee. Subquadratic Space-Complexity DigitSerial Multipliers Over GF (2m) using Generalized (a,b)-way Karatsuba Algorithm, IEEE Transactions on Circuits and Systems –I. 2015; 62(4):1091−98.
  • Zhi-Hong Mao. High –Throughput Digit-Serial Systolic Multiplier Over GF (2m) Based on Irreducible Trinomials, IEEE Transactions on Circuits and Systems –II. 2015; 62(5):481−85.
  • Xie J, Meher PK. Low Latency Systolic Montgomery Multiplier for Finite Field GF (2m) based on Pentanomials, IEEE Trans. on VLSI Syst. 2013; 21(2).
  • Cantor DG. On Arithmetical Algorithms over Finite Fields, Journal of Combinatorial Theory, Series A. 1989; 285−300.


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