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Register Embedded Self Immunity using Reversible Logic Gates

Affiliations

  • Department of Electronics and Communication Engineering, GMR Institute of Technology, Rajam – 532127,Andhra Pradesh, India

Abstract


Now days due to Continuous shrinkage in number of transistors on chip, soft errors also increases. Soft errors are very annoying because they are an energetic particle which propagates in entire system causing transient faults. This in turn reduces the Reliability of register files. In this paper Self-Immunity Technique is introduced, which improves register file Reliability with respect to soft errors. In this paper difficulty to enhance the register file integrity against soft errors based on the observation. In this paper, Reversible Logic Gates (RLG) is used instead of Logic Gates to design the circuit and Error Correcting Code (ECC) is incorporated within the circuit to avoid soft errors. Our Experiments demonstrate that our proposed technique reduced Power consumption by 30.51%, Delay in time reduced by 12.6% and Temperature decreased by 0.1%.

Keywords

ECC- Error Correcting Code, RESI- Register Embedded Self Immunity, RLG- Reversible Logic Gates.

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References


  • Amrouch H, Ebi T, Henkel J. RESI: Register-Embedded SelfImmunity for reliability enhancement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2014 May; 33(5):677–90.
  • Amrouch H, Henkel J. Self-immunity technique to improve register file integrity against soft errors. In the Proceedings of 24th Internatioal Conference on VLSI Design, Institute of Electrical and Electronics Engineers(IEEE). 2011 Jan. p.189–94.
  • Shukla V, Singh OP, Mishra GR. A novel approach to design a redundant binary signed digit adder cell using RLG. In IEEE UP Section Conference on Electrical Computer and Electronics (UPCON), Institute of Electrical and Electronics Engineers(IEEE); 2015 Dec. p. 1–6.
  • Suresh R, Kumar TRD, Bennet MA, Thamu, Santhosh, Sudhakharan. Low power high speed performance of multiplexer using reversible logic. Middle-East Journal of Scientific Research 24 (Techniques and Algorithms in Emerging Technologies). 2016:362–8.
  • Jongeun Lee and Aviral Shrivastava, “A Compiler Optimization to Reduce Soft Errors in Register Files,” in Proceedings of the ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems; LCTES. Dublin, Ireland; 2009 Jun. p. 41–49.
  • Rahman MdS, Waheed S, Bahar AN. Optimized design of full-subtractor using new SRG RLG and VHDL simulation.In International Conference on Electrical and Electronic Engineering (ICEEE). 2015 Nov 04–06.
  • Gupta Y, Sasamal TN. Implementation of RLG using adiabatic logic. In Power, Communication and Information Technology Conference (PCITC), Institute of Electrical and Electronics Engineers(IEEE); 2015 Oct. p. 595–98.
  • Lee J, Shrivastava A. Compiler-managed register file protection for energy-efficient soft error reduction.In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC); 2009. p. 618–23.

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