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Improving Testability of Design in FPGA using Raspberry Pi

Affiliations

  • Electronics and Communication Engineering, SRM University, Vadapalani, Chennai - 600026, Tamil Nadu, India
  • Electronics and Communication Engineering, BSAU University, Chennai - 600048, Tamil Nadu, India

Abstract


Objective: To implement a logical approach for providing better ability to observe and control FPGA pins through Raspberry Pi for functional verification of FPGA based system design. Method/Analysis: It mainly involves improving the testability of design in FPGA using Raspberry Pi. Findings: The use of Raspberry Pi makes the controllability and observability of FPGA pins easy and the inputs, outputs of FPGA can be remotely controlled via Webiopi which is a web interface for Raspberry Pi. Novelty/Improvement: The web interface is also used to start the BIST and to test the FPGA with test vectors any times.

Keywords

ATE, BIST, FPGA, Raspberry Pi, Webiopi.

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References


  • Blodget B, James-Roxby P, Keller E, McMillan S, Sundararajan P. A self-reconfiguring platform. Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL’03); 2003 Sep. p. 565–74.
  • Fiethe B, Michalik H, Dierker C, Osterloh B, Zhou G. On reconfigurable system-on-chip data processing units for miniaturized space imaging instruments. ACM; 2007. p.977–82. ISBN 978-3-9810801-2-4.
  • Nathan D, Lim K, Choo K, Wong P, Weisensee A. A high level reconfigurable computing platform software frameworks, arXiv.org cs.AR/0405015; 2004 May.
  • Ullmann M, Huebner M, Grimm B, Becker J. A FPGA runtime system for dynamical on-demand reconfiguration.RAW04; Santa Fe. 2004 Apr.
  • Vidya Sagar D, Vyshnavi Vihitha G. WebIOPi - Remote controlled robot cam using rest framework. International Journal of Emerging Research in Management and Technology.2015; 4(8):73–7. ISSN: 2278-9359.
  • Wang S, Gupta S. DS-LFSR: A new BIST TPG for low heat dissipation. Proc Int Test Conf. (ITC’97); 1997. p. 848–57.
  • Thameema Begum J, Harshavardhan Naidu S, Vaishnavi N, Sakana G, Prabhakaran N. Design and implementation of reconfigurable ALU for signal processing applications.Indian Journal of Science and Technology. 2016 Jan; 9(2).
  • Hertwig A, Wunderlich HJ. Low power serial built-in selftest.Proc IEEE Eur Test Workshop; 1998 May. p. 49–53.
  • Karthik S, Shreya, Viswanath, Srihari. Remote FPGA Lab.International Journal of Research Engineering and Technology.2014 Jul. eISSN: 2319-1163 | pISSN: 2321-7308.
  • Karthik S, Prasanna vishal TR, Jayaram SG, Priyadarsini K.GSM based FPGA configuration. IOSR Journal of VLSI and Signal Processing (IOSR-JVSP). 2014 Jul-Aug; 4(4):58–61.e-ISSN: 2319–4200, p-ISSN No: 2319–419.

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