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Efficient CPU Core Usage and Balanced Bandwidth Distribution using Smart Adaptive Arbitration


  • School of Electrical and Electronics Engineering, Universiti Sains Malaysia, 14300 Nibong Tebal, Penang, Malaysia


Software industry has been revolutionized due to the introduction of multi-core chips and high performance computing. The current trend shows that number of cores per chip will double every alternate year without any modification in the processor clock speed. Sophisticated parallel computation needs to resolve the access of bus in an optimum manner by keeping in mind the parameter of efficiency. In any multi-core system, an arbiter is the one which receives numerous bus access requests which various processors (masters) generates. This article proposes a new strategy of arbitration known as Smart Adaptive Arbitration (SAA) to enhance the CPU cores usage to enable parallel computing along with balanced bus bandwidth distribution. The designed SAA is for heterogeneous masters which compute with respect to different behavior of data traffic to attain task parallelism. Latest benchmark program has been used to evaluate the performance of SAA. The results shows that SAA stands better if compared with other arbitration techniques as it tries to enable high degree of task parallelism and a balanced bandwidth distribution to the masters requesting bus access. SAA has a potential to be a promising arbitration strategy for solving future on-chip resource necessities.


Arbiter, Bandwidth Distribution, CPU Utilization, Multi-Core, Smart Adaptive Arbiter, Task Parallelism.

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  • Pasricha S. and Dutt N. Communication ArchitecturesSystem On-Chip Interconnect. USA: Morgann Kaufmann: 2008.
  • Poletti F, Bertozzi D, Benini L and Bogliolo A. Performance Analysis of Arbitration Policies for SoC Communication Architectures. Design Automation for Embedded Systems. 2003 June; 8(1):189-210. Available from:
  • Wiseman Y and Feitelson DG. Paired gang scheduling. Parallel and Distributed Systems, IEEE Transactions. 2003; 14(1):581-92.
  • Samman FA. Runtime connection-oriented guaranteedbandwidth network-on-chip with extra multicast communication service. Microprocessor and Microsystem. 2014; 38(1):170-81. Available from: https://doi.
  • org/10.1016/j.micpro.2013.07.006.
  • Yaashuwanth C and Ramesh. Intelligent time slice for round-robin in real time operating systems. IJRRAS. 2010; 2(1):126-31.
  • Vilas N and Shyam L. Time Efficient Arbiter in the design of Scheduler embodying ISLIP algorithm for on chip interconnection. IJAST. 2010; p. 2005-13.
  • Davidovic T. and Crainic TG. Parallel Local Search to schedule communicating tasks on identical processors. Parallel Computing. 2015; 48(1):1-14. Available from:
  • Chang Hee P, Chi Ho L, Hi Seok K and Jong Wha C. The efficient bus arbitration scheme in SoC environment. 3rd Workshop IEEE System-on-Chip for Real-Time Applications. 2003; p. 311-5.
  • Lahiri K, Raghunathan A and Lakshminarayana G. LOTTERYBUS: A new high-performance communication architecture for system-on-chip designs. Proceedings, Design Automation Conference. 2001; p. 15-20.
  • Yi X, Li L, Ming-Lun G, Bing Z, Zhao-Yu J, Gao-Ming D. An Adaptive Dynamic Arbiter for Multi-Processor SoC. 8th International Conference on Solid-State and Integrated Circuit Technology. 2006; p. 1993-6.
  • Aravind A. An arbitration algorithm for multiport memory systems. IEICE Electronics Express. 2005; 2(1):488-94. Available from:
  • Massimo E and Poncino M. The design of easily scalable bus arbiters with different dynamic priority assignment schemes. Italy: IEEE-Signals, Systems and Computers. 1995; p. 211-3.
  • JR. Lopez-Blanco, Reyes R, Aliaga JI, Badia RM, Chacon P and Quintana-Orti ES. Exploring large macromolecular functional motions on clusters of multicore processors. Journal of Computational Physics. 2013 Aug; 246(2):275-88. Available from:
  • Chien-Hua C, Geeng-Wei L, Juinn-Dar H and Jing-Yang J. A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. Design Automation. Asia and South Pacific Conference. 2006; p. 24-7. Available from:
  • Li H, Ming Z, Wei Z and Dongxiao L. An Adaptive Arbitration Algorithm for SoC Bus. NAS International Conference on Networking, Architecture, and Storage. 2007; p. 245-6. Available from:
  • Nejati S, Alesio SD, Sabetzadeh M and Briand L. Modeling and analysis of CPU usage in safety-critical embedded systems to support stress testing. Innsbruck, Austria: The Proceedings of the 15th international conference on Model Driven Engineering Languages and Systems. 2012; p. 759-75. Available from:
  • Shuai C, Boyer M, Jiayuan M, Tarjan D, Sheaffer JW, Sang-Ha L. Rodinia: A benchmark suite for heterogeneous computing. IEEE International Symposium on Workload Characterization, IISWC. 2009; p. 44-54.
  • Enzo Rucci AD, Franco Chichizola, Marcelo Naiouf, Laura de Giusti. DNA sequence alignment: hybrid parallel programming on a multicore cluster. Recent Advances in Computers, Communications, Applied Social Science and Mathematics, WSEAS. 2011; p. 183-90.
  • Kerdprasop K. Parallelization of K-Means Clustering on Multi-Core Processors. Selected topics in applied computer science. WSEAS. 2010. p. 472-77.
  • Baek N and Lee H. Implementing Matrix Multiplications on the Multi-Core CPU Architectures. Hangzhou, China: Proceedings of the 6th WSEAS International Conference on Applied Computer Science. 2007; p. 431-5.
  • Cutting D and Cafarella M. Hadoop Framework. USA Patent. 2009.
  • Akhtar MN, Sidek O. An Intelligent Adaptive Arbiter for Maximum CPU Utilization, Fair Bandwidth Allocation and Low Latency. IETE Journal of Research. 2013; 59(2):48-52. Available from:
  • McCalpin JD. Memory bandwidth and machine balance in current high performance computers. IEEE Computer Society Technical Committee on Computer Architecture, TCCA. 2016; p. 19-25.


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