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Design and Implementation of FPGA Based Digital Base Band Processor for RFID Reader
RFID ipso facto deals with identification of objects through radio waves. Its use started during World War II in the identification of “Friend-or-Foe” for targets used by the military, such as aircraft and forces. It was only in 1990s, that large scale use of RFID started. The objective of this paper is to implement the digital baseband processor for UHF RFID reader compatible with EPC Global C1G2 /ISO 18000-6 C protocol. The functional simulation of digital base band processor is done using Modelsim simulator. It is verified and tested successfully on FPGA Spartan-6 prototype board for its logic function. A new bit stream encoding and decoding module are presented for the digital base band processor. The synthesis results proved, that the power consumption of the digital base band processor is about 5mW and the number of slice registers and LUTs used are 32 and 33 respectively. The results presented in this paper are better than literature reported in terms of power. Areas of use RFID were supply management, for tracking articles, inventory and also for identification of animals.
CRC, FPGA, HDL, ISO18000-6, RFID, UHF Reader
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