Total views : 273

Improving breakdown voltage in LDMOS with doped silicon pockets in buried oxide

Affiliations

  • EPCET, Jnana Prabha, Virgo Nagar Post, Aavalahalli, Bengaluru - 560049, Karnataka,, India
  • KVGCE, Kurunjibhag, Sullia - 574327, Karnataka,, India

Abstract


An SOILDMOS device with a new technique of having doped silicon pockets in SOI buried oxide is presented in this paper. The doped silicon pockets reduce the effective electric field in the top silicon layer by forming a depletion region between the pockets and the drift region, thereby improving the device breakdown voltage and reducing specific resistance. The device simulations are carried out in an open source TCAD software package. The effective values of doping, device geometry is found and the device structure is developed. The modeled device gives a breakdown voltage of 79.5V, specific resistance of 23.4mΩ-mm2 and FOM of 27MW/cm. The device is shown to have a threshold voltage of 4V making it suitable for high voltage technology. Performance comparison with currently available Commercial LDMOS devices is also presented.

Keywords

Breakdown Voltage, Doped Silicon Pockets, Figure of Merit (FOM), RESURF, SOI-LDMOS, Specific Resistance

Full Text:

 |  (PDF views: 344)

References


  • Dye N, G. H. Radio Frequency Transistors: Principles and Practical Applications. Newness. 2001.
  • van Rijs F, S.T. Efficiency improvement of LDMOS transistors for base stations: towards the theoretical limit. 2006; p. 205-8.
  • Rjis, FV. Status and Trends of Silicon LDMOS base station PA technologies to go beyond 2.5 GHz applications.RWS2008, p. 69-72.
  • Bill V. APMC 2005, Comparative Analysis of GaAs/LDMOS/ GaN High Power Transistors in a Digital Predistortion Amplifier System. 2005.
  • Hazel M. Semiconductor TCAD Fabrication Development for BCD Technology. 2006.
  • Sigg HJ, Vendelin GD, Cauge TP and Kocsis J. D-MOS Transistor for Microwave applications. IEEE T. Electron Dev.1972; ED-19(1):45–53.
  • Ludikhuize AW: A review of RESURF Technology. Proc.Int. ISPSD Conf. 2000. 2000; p. 11–18.
  • Smayling MC, T.M. Patent No.US Patent 5585294. 1996.
  • Mosher DM, E.T. Patent No.US Patent 6483149. 2002.
  • Formicon G, B. B. A 130WLDMOS for 2.7-3.5 GHz Broadband Radar Applications. Proceedings of the 6th EuropeanMicro wave Integrated Circuits. 2011.
  • A, K. High Power LDMOS Transistor for RF Amplifiers. ProceedingsofInternationalBhurbanConferenceonAppliedSciences andTechnology. 2007.
  • Bawedin M, Renaux C, Flandre D. LDMOS in SOI Technology with very thin silicon film. Solid-State Electron. 2007; 48(2004):2263–70.
  • DeSouza MM, Cao G, Narayanan EMS, Youming F, Manhas SK, Luo J and Moguilnaia N. Progress in silicon RF power MOS technologies-current and future trends: Aruba: Proceedings of the 4th IEEE Int. Caracas Conf. Devices, Circuits Syst. 2002; p. D047-1-7.
  • Arnold E. Silicon on Insulator Devices for High Voltage and power IC applications. J. Electrochem. Soc. 1983; 141(1994).
  • Antognetti P. McGraw-Hill: Power Integrated Circuits: Physics, Design and Applications. 1986.
  • Ludikhuize AW. A Review of RESURF Technology, Proc.ISPSD. 2000; p. 11–18.
  • Oruji AA, Mehrad M. The best control of parasitic BJT effect in SOI-LDMOS with SiGe window under channel.IEEE Trans. Electron Devices. 2012; 59:419–25.
  • Mehrad M, Orouji AA. Injected charges in partial SOI LDMOSFETs: A new technique for improving the breakdown voltage Superlattices Microstruct. 2013; 57:77–84.
  • Han MH, Chen HB, Chang CJ, Tsai CC and Chang CY. Improving Breakdown Voltage of LDMOS Using a Novel Cost Effective Design. IEEE Transactions on Semiconductor Manufacturing. 2013 May; 26(2):248-52.
  • Haynie S. Power LDMOS with novel STI profile for improved Rsp, BVDSS and reliability. ISPSD Hiroshima. 2010 June; p-241-44.
  • Huang TY. et al. 0.18um BCD technology with best-in-class LDMOS from 6V to 45V. Waikoloa, HI: 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC’s (ISPSD). 2014; p.179-81.
  • Cristoloveanu S.Silicon on insulator technologies and devices: from present to future. Solid State Electron. 2001; 45:1403–11.
  • Orouji AA, Mehrad M. Breakdown voltage improvement of LDMOSs by charge balancing: An inserted P-layer intrenchoxide (IPT- LDMOS), Super lattices Microstruct. 2012; 51(3):412-20.
  • Zareiee M, Orouji AA & Mehrad MJ. A novel high breakdown voltage LDMOS by protruded silicon dioxide at the drift region. Journal of Computational Electronics. 2016: 15(2):611-18.
  • Sunitha HD, Keshaveni N. Modeling and Simulation of LDMOS Device. International Journal of Engineering Research. 2015; 4(6):291-95.
  • Bawedin M, Renaux C, Flandre D. LDMOS in SOI technology with very-thin silicon film’. Solid-State Electronics. 2004; 48(12):2263-70.
  • Sunitha HD, Keshaveni N. Improved Breakdown Voltage LDMOS. International Journal of Engineering Research. 2015; 4(6):291-95.

Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.