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Improving breakdown voltage in LDMOS with doped silicon pockets in buried oxide


  • EPCET, Jnana Prabha, Virgo Nagar Post, Aavalahalli, Bengaluru - 560049, Karnataka,, India
  • KVGCE, Kurunjibhag, Sullia - 574327, Karnataka,, India


An SOILDMOS device with a new technique of having doped silicon pockets in SOI buried oxide is presented in this paper. The doped silicon pockets reduce the effective electric field in the top silicon layer by forming a depletion region between the pockets and the drift region, thereby improving the device breakdown voltage and reducing specific resistance. The device simulations are carried out in an open source TCAD software package. The effective values of doping, device geometry is found and the device structure is developed. The modeled device gives a breakdown voltage of 79.5V, specific resistance of 23.4mΩ-mm2 and FOM of 27MW/cm. The device is shown to have a threshold voltage of 4V making it suitable for high voltage technology. Performance comparison with currently available Commercial LDMOS devices is also presented.


Breakdown Voltage, Doped Silicon Pockets, Figure of Merit (FOM), RESURF, SOI-LDMOS, Specific Resistance

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