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VLSI Implementation of Low Power and High Speed Architecture of DWT-IDWT using Lifting based Algorithm

Affiliations

  • Visvesvaraya Technological University, “Jnana Sangama”, Belagavi – 590018, Karnataka,, India
  • Cambridge Institute of Technology, SR Layout, Chikkabasavanapura, Krishnarajapura, Bengaluru – 560036, Karnataka,, India

Abstract


Objective: The purpose of this study is to optimize DWT1-IDWT2 architecture for different Image Compression techniques using lifting based algorithms. Statistical Analysis: The data in form of image and video are transmitted as signal. Because of limited channel bandwidth the data has to be compressed and this reduces the quality of the image. An algorithmic concept of encoding information is given by wavelets in a manner that is layered according to level of detail. The analysis of this implementation includes speed optimization, accuracy, and power reduction. This study uses pipelined architecture of 1D-DWT architecture and is combined with another 1D-DWT module in parallel to obtain 2D-DWT architecture to analyze the speed. Findings: The study was done using VLSI cad tools and coding was done using Verilog, by implementing the proposed algorithm with pipelined-parallel architecture for image compression using DWT, we analyzed the timing wrt* clock speed and we analyzed PSNR and SNR for different video and image compression techniques. Improvements: Our study shows higher speed can be achieved by using DWT for image compression and by using VLSI architecture, the study can be optimized to any further extent.

Keywords

Compression, DWT, IDWT, Lifting Algorithm, Low Power

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