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VLSI Implementation of Low Power and High Speed Architecture of DWT-IDWT using Lifting based Algorithm
Objective: The purpose of this study is to optimize DWT1-IDWT2 architecture for different Image Compression techniques using lifting based algorithms. Statistical Analysis: The data in form of image and video are transmitted as signal. Because of limited channel bandwidth the data has to be compressed and this reduces the quality of the image. An algorithmic concept of encoding information is given by wavelets in a manner that is layered according to level of detail. The analysis of this implementation includes speed optimization, accuracy, and power reduction. This study uses pipelined architecture of 1D-DWT architecture and is combined with another 1D-DWT module in parallel to obtain 2D-DWT architecture to analyze the speed. Findings: The study was done using VLSI cad tools and coding was done using Verilog, by implementing the proposed algorithm with pipelined-parallel architecture for image compression using DWT, we analyzed the timing wrt* clock speed and we analyzed PSNR and SNR for different video and image compression techniques. Improvements: Our study shows higher speed can be achieved by using DWT for image compression and by using VLSI architecture, the study can be optimized to any further extent.
Compression, DWT, IDWT, Lifting Algorithm, Low Power
- Fei Wu B, Fu Lin C. A high-performance and memoryefficient pipeline architecture for the 5/3 and 9/7 discrete wavelet transform of JPEG2000 codec Circuits and Systems for Video Technology, IEEE Transactions. 2005 Dec; 15(12):1615-28.
- Cao P, Guo X, Wang C, Li J. Efficient architecture for twodimensional discrete wavelet transform based on lifting scheme.7th International Conference-ASICON -07. 2007 October.
- Manzoor RS, Gani R, Jeoti V, Kamel N, Asif M.Implementation of FFT using discrete wavelet packet transform (DWPT) and its application to SNR estimation in OFDM systems. Kaula Lumpur, Malaysia: IEEE International Symposium on Information Technology. 2008.
- Bouwel CV. Wavelet Packet Based Multicarrier Modulation.IEEE Communications and Vehicular Technology. 2000; p.131-38.
- Al-Azawi S, Abbas Y, Jidin R. Low complexity multidimensional CDF 5/3 DWT architecture. 2014 9th International Symposium Communication Systems, Networks & Digital Signal Processing (CSNDSP). 2014 July.
- Yifan S, Xiao S, Xiong Y, Hao S, Zhao X. Time-frequency analysis system based on temporal Fourier transform, in 2015 IEEE International Conference on Communication Problem-Solving (ICCP), Guilin, 2015.
- S. S. Bhairannawar, S. Sarkar, K. B. Raja, K. R. Venugopal.An Efficient VLSI architecture for fingerprint recognition using O2D-DWT architecture and modified CORDIC FFT. Signal Processing, Informatics, Communication and Energy Systems (SPICES). 2015 Feb 19-21.
- Chetan H, Indumathi G. Low power VLSI implementation of data compression for multimedia devices using CDF m/n DWT on to resource constrained dynamically reconfigurable memories. New Delhi: 2016 3rd International Conference on Computing for Sustainable Global Development (INDIACom). 2016.
- Baig S, Rehman FU, Mughal MJ. Performance comparison of DFT, discrete wavelet packet and wavelet transforms.OFDM transceiver for multipath fading channel, Multitopic Conference. 2005.
- Lakshmananm MK, Nikookar H. A review of wavelets for digital wireless communication. Springer: Journal on Wireless Personal Communication. 2006; 37(3-4):387-420.
- Kang Lai Y, Fei Chen L, Chih Shih Y. A high-performance and memory efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform, Consumer Electronics. IEEE Transactions. 2009 May; 55(2): 400-07.
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