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Design and Implementation of a Five Stage Pipelining Architecture Simulator for RiSC-16 Instruction Set


  • Department of Electrical and Computer Engineering, IIUM, Malaysia
  • Department of Electrical and Computer Engineering, Ahmadu Bello University, Zaria, Nigeria
  • Department of Information Technology, Central University of Kashmir, Srinagar–190015, Jammu and Kashmir, India


In modern computing, multitasking is the most favorable aspect. An un-pipelined instruction cycle (fetch-execute cycle) CPU processes instructions one after another increasing duration at lesser speed in completing tasks. With pipelined computer architecture, unprecedented improvement in size and speed are achievable. This work investigates the possibility of a better improvement to computer architecture through understanding the inner workings of instruction pipelining in operating system. A design of a 5 stage pipelined architecture simulator for RiSC-16 processors using Visual Basic programming has been achieved contrary to the common available four stage simulators. The simulator also future two most common pipeline instruction hazards generally missing in most available simulators. Thus, the designed simulator becomes an appropriate tool for understanding the concept of pipelining on a step-by-step visualization based instructioncycle processors hence facilitating a more efficient design in computer architecture. The simulator has been evaluated based on its closeness to real time pipelined computer architecture and through execution of all 8 basic RiSC-16 instruction set with data dependency and control hazard.


Computer Processor & Architecture, Instruction Pipelining, RiSC-16 Simulator

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  • Rakesh MR, Ajeya B, Mohan AR. Novel architecture of 17 bit address RISC CPU with pipelining technique using Xilinx in VLSI Technology. International Journal of Engineering Research and Applications.2014; 4(5):116–121.
  • Rakesh MR.Design and simulation of four stage pipelining architecture using the Verilog. International Journal of Science and Research. 2014; 3(3):108–12.
  • Rana S, Mehra R. Design &simulation of RISC processor using hyper pipelining technique. IOSR Journal of Mechanical and Civil Engineering (IOSR-JMCE). 2013; 9(2):49–57.
  • Trivedi P. Design &analysis of 16 bit RISC processor using low power pipelining. 2015 International Conference on Computing, Communication & Automation (ICCCA); 2015:1294–7.
  • Finlayson I, Uh GR, Whalley DB, Tyson G. An overview of static pipelining. IEEE Computer Architecture Letters.2012; 11(1):17–20.
  • Cheah HY, Fahmy SA, Kapre N. Analysis and optimization of a deeply pipelined FPGA soft processor. 2014 International Conference on Field-Programmable Technology(FPT); 2015. p. 235–8.
  • Hoganson KE. High-performance computer architecture and algorithm simulator. Journal on Educational Resources in Computing. 2002; 2(1):131–48.
  • Grunbacher H. Teaching computer architecture/organisation using simulators. 28th Annual Frontiers in Education Conference, FIE’98. Treitlstrasse Vienna Austria. 1998; 3:1107–12.
  • Osée M, Richard A, Biest AV, Mathys P. Educational simulation of the RiSC processor. International Conference on Engineering Education(ICEE 2007); 2007.
  • Hoganson K. The unified parallel speedup model and simulator.Southeast Regional ACM Conference; 2001. p. 1–23.
  • Balasubramonia R. CS6810 computer architecture. University of Utah: Youtube; 2012.
  • Jacob PB. The pipelined RiSC-16. ENEE 446: Digital Computer Design, Fall 2000; 2000. p. 1–9.


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