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Subthreshold FinFET SRAM at 20nm Technology with Improved Stability and Lower Leakage Power
Background/Objectives: The Complementary Metal–Oxide–Semiconductor (CMOS) scaling feature was the wonderful feature which led the electronics market into in an era of miniaturization but with the fascinating feature some limitations has also been observed. Methods/Statistical analysis: CMOS technology has also given a new horizon to the memory circuits like Static Random-Access Memory (SRAMs). To overcome the limitations of scaling of the CMOS technology, Fin Field Effect Transistor (FinFET) technology has been chosen. To overcome the limitations of scaling of the CMOS technology, FinFET technology has been chosen. Like CMOS SRAMs, FinFET SRAMs have also gained popularity because of the advantages as discussed in this paper. Findings: In this paper, FinFET SRAM cells have been proposed in three different configurations for better stability and reduced leakage power in sub threshold region at 20nm technology.4 different modes of FinFET has been used to implement the SRAM. The FinFETs are classified as (i) SG-mode (ii) LP-mode and (iii) IG mode. A comprehensive analysis has been made for all the 4 types of SRAM stability which includes for Read Margin, Write Margin, Hold Margin and leakage power analysis by finding the leakage current for all the proposed circuits and has compared with the previous work and it has been found that the proposed circuits serves better in terms of stability and reduced leakage current. The cell has been implemented for sub threshold voltages ranging from 0.4V to 0.1V. The maximum Write Margin at 0.4V is 196.9mV, Read Margin is 110 mV. Application/Improvements: It has been found that from the different SRAM circuits, IG-P has the maximum Write SNM, Read SNM and hold margin while LP mode has minimum leakage current, next the IG-P mode FinFET.
FinFET, Leakage Current, Read Margin, SRAM, Write Margin.
- Chauhan YS, Lu D, Vanugopalan S, Khandelwal S, Duarte JP, Paydavosi N, Niknejad A, Hu C. FinFET modeling for IC simulation and design using the BSIM-CMG standard. Elsevier; 2015 Feb 18. p. 135–80.
- Cakici T, Kim K, Roy K. FinFET based SRAM design for low standby power applications. In the Institute of Electrical and Electronics Engineers (IEEE) Proceedings of the 8th International Symposium on Quality Electronics Design (ISQED), San Jose, CA, USA; 2007 Mar. p. 127–32.
- Ma K, Liu H, Xiao Y, Zhang Y, Li X, Gupta SK, Xie Y, Narayan V. Proceedings of the IEEE Computer Society Annual Symposium on VLSI, Tampa, Florida, USA; 2014. p. 9–14.
- Ebrahimi B, Afzalikusha A, Mahmoodi H. Robust FinFET SRAM design based on dynamic back gate voltage adjustment. Microelectronics Reliability. 2014; 5:2604–12.
- Salahuddin SM, Chan M. Eight-FinFET fully differential SRAM cell with enhanced read and write voltage margins. Institute of Electrical and Electronics Engineers (IEEE) Transaction on Electron Devices. 2015; 62(6):2014–21.
- Gupta SK, Kulkarni J, Roy K. Tri-mode independent gate FinFET based AM with pass gate feedback: technology circuit co-design for enhanced cell stability. Institute of Electrical and Electronics Engineers (IEEE) Transaction on Electronics Devices, 2013; 60(11):3696–704.
- Tawkif SA, Kursun V. Robust FinFET memory circuits with p-type data access transistors for higher integration density and reduced leakage power. Journal of Low Power Electronics. 2009; 5:497–508.
- Zeinali B, Madsen JK, Raghavan P, Moradi F. Sub-threshold SRAM design in 14 Nm FinFET technology with improved access time and leakage power. Proceedings of Institute of Electrical and Electronics Engineers (IEEE) Computer Society Annual Symposium on VLSI, Montpellier, France; 2015 Jul. p. 74–9.
- Patel KSV, Bhushan HN, Gadag KG, Prasad BNN, Haroon M. Low power Schmitt trigger based SRAM using 32NM FinFET devices. International Journal of Computer, Electrical, Automation, Control and Information Engineering. 2014; 8(2):383–6.
- Calhoun BH, Chandrakasan AP. Static noise margin variation for sub-threshold SRAM in 65-nm CMOS. Institute of Electrical and Electronics Engineers (IEEE) Journal of Solid State Circuits. 2006; 41(7):497–502.
- Jha NK, Chen D. Nano electronic circuit design. Springer Science; 2011. p. 50–70.
- Birla S, Shukla NK, Pattanaik M, Singh RK. Analysis of 8T SRAM cell at various process corners at 65nm process technology. Circuits and Systems; 2011. p. 11–6.
- Birla S, Singh RK, Pattanaik M. Static noise margin analysis of various SRAM topologies. IACSIT Journal of Engineering & Technology. 2011 Jun; 3(3):304–9.
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