Total views : 260

Survey on Multigrained Reconfigurable Architecture using Parallel Mapping Method


  • Department of ECE, KL University, Green Fields, Vaddeswaram, Guntur – 522502, Andhra Pradesh, India
  • Department of ECE, Guntur Engineering College, NH 5, Opposite Katuri Medical College, Yanamadala, Guntur - 522019, Andhra Pradesh, India


Objectives: In previous methodology, only ALU operations are seen with respect to the network on chip with this power and delay is high whereas in present research, Multi-grained reconfigurable architecture is used which reduces power and delay. In this method we can also perform multiple FFT, DCT, FIR and channel encoder. Methods: For execution, the number of instructions is flapped by associating pipelining technique which is splitted in stages. Every stage completes an area of parallely connected instructions at a time. A pope is created, with the interconnection of stages where instructions are fed at amend, progresses through these stages and exits at other end. The group of Function Units (FU'S) was connected in a mesh style network in CGRA'S. Here, the subsets of FU's are accessed only with help of segregation of register files through CGRA's that which carries temporary values. In general word operations like addition, subtraction and multiplication were carried out by these function units. Findings: For better execution characteristics of parallel mapping on MGRA, more PE utilisation rate and less memory access overhead are considered as resulting conditions. Lastly, Multi Grained Reconfigurable Architecture (MGRA) is the proposed research work where processing element consists of a multiple operations like FFT, DCT, FIR, Channel Encoder etc. The proposed architectures require multiple processing elements to execute parallel process as to reduce PE's complexity. A new folding tree algorithm is proposed (MGRA) with CRGA is proposed to eliminate PE's. This method reutilizes PE's to redistribute data from multiple nodes and the controller is integrated with current CGRA to scan the processing nodes with common expression executions. By using nested loop pipelining the Multi grained reconfigurable architecture comprises the advantages of low power and delay when compared to the existing architectures. Application: MGRA used in communication, digital signal processing.


CGRA, Multi-Grained Reconfigurable Architecture (MGRA), Network-on-Chip, Parallel Mapping, Reconfigurable Computing.

Full Text:

 |  (PDF views: 176)


  • Hartenstein R, Grunbacher H. A The Roadmap to Reconfigurable computing. Springer-Verilog: Proceedings of Field-Programmable Logic and Applications. 2000 Aug; 27–30.
  • Ahmad Alsolaim, Jurgen Becker. A dynamically reconfigurable system-on-a-chip architecture for future mobile digital signal processing. European Signal Processing Conference. 1999.
  • Bindra A. Reconfigurable architectures chart a new course for DSPs. Electronic Design. 2002 August 5; p. 46–52.
  • Hartenstein R. A decade of reconfigurable computing: A visionary retrospective. Proceedings of the Design, Automation and Test in Europe. 2001; p. 642-49.
  • Weinhardt M and Luk W. Pipeline vectorization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2001 February; 20:234-48.
  • Bondalapati K and Prasanna K. Loop pipelining andoptimization for run-time reconfiguration. Reconfigurable Architectures Workshop. 2000.
  • Singh H, et al. MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications.IEEE Transactions of Computers. 2000 May; 49(5):465-81.
  • Compton K. Northwestern University, Department of Electrical and Computer Engineering: Architecture Generation of Customized Reconfigurable Hardware, Doctor of Philosophy Thesis. 2003.
  • Bouwens F, Berekovic M, De Sutter B, Gaydadjiev G. Architecture enhancements for the ADRES coarsegrained reconfigurable array. Berlin, Germany: Springer-Verlag: High Performance Embedded Architectures and Compilers. 2008; p. 66-81.
  • Lee J, Choi K, Dutt N. Compilation approach for coarsegrained reconfigurable architectures. IEEE Design and Test of Computers. 2003 January/February; 20:26-33.
  • Cardoso J and Weinhardt M. Fast and guaranteed C compilation onto the PACT-XPPTM reconfigurable computing platform. The Proceedings of Field-Programmable Custom Computing Machines. 2002; 291–92.
  • Bondalapati K. Parallelizing DSP nested loops on reconfigurable architectures using data context switching. The Proceedings of Design Automation Conference. 2001; 273-76.


  • There are currently no refbacks.

Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.