Total views : 429
Neural Network Architecture for Hybrid Network-On-Chip using Scalable Spiking for Man Machine Interface
Hardware-based computer vision accelerators are going to be an important part of future mobile devices to satisfy the low power and data processing demand. In order to comprehend a high power potency and high turnout, the accelerator design will be massively parallelized and tailored to vision process that is a plus over software-based solutions and all-purpose hardware. In this research Spiking neural networks (SNNs) arrange to emulate scientific discipline within the class brain supported neurons parallel arrays that communicate through spike events. The opportunity to perform embedded neuromorphic circuits is supplied by SNNs, with low power consumption and high correspondence in comparison with the normal laptop paradigms of John von Neumann. Even so, the poor property and modularity shortage as shown in ancient neuron cell interconnect implementations supported shared bus topologies is barring climbable hardware operations of SNNs. In order to effectively apply SNN traffic patterns and neighborhood among neurons in the current design the Hybrid Network on Chip (H-NoC) design integrates a spike traffic compression technique, thus dropping traffic overhead and up turnout on the network provides world traffic hundreds to sustain turnout underneath bursting activity. The planned system reduces overhead and improves the performance through native routing of the neutron cell facilities that are the gifts within constant tile facility. This will increase the potency of the system. The scalability of the adopted H-NoC approach under completely different situations is shown by analytical results show, while synthesis and simulation analysis reveal, area of low-cost, and delay for each cluster severally. This methodology finds its application in various sector such as medical image processing and bio signal processing.
Hybrid Network, Hybrid Network on Chip, Neural Network, Scalable Spiking, Spiking Neural Network.
- Dally WJ, Towles B. Route packets, not wires: on-chip interconnection networks. Proceedings of the 38th Design Automation Conference, Las Vegas, Nev, USA: June 2001. p. 684–9. Crossref
- Design Automation Conference, 2001. p. 684–9.
- Theocharides T, Link G, Vijaykrishnan N, Invin M, Srikantam V. A Generic Reconfigurable Neural Network Architecture as a Network on Chip. Proc. IEEE Int’l SOC Conf., 2004 Sep. p. 191–4. Crossref
- Emery R, Yakovlev A, Chester G. Connection-Centric Network for Spiking Neural Networks. Proc. Third ACM/ IEEE Int’l Symp. Networks-on-Chip, 2009 May. p. 144–52. Crossref
- Harkin J, Morgan F, McDaid L, Hall S, McGinley B, Scaly. A Reconfigurable and Biologically Inspired paradigm for Computation Using Network-on-Chip and Spiking Neural Net-works. Int’l J. Reconfigurable Computing. 2009; 1–13. Crossref
- Carrillo S, Harkin J, Media L, Pande S, Cawley S, McGinley B, Morgan F. Advancing Interconnect Density for Spiking Neural Network Hardware Implementations Using TrafficAware Adaptive Network-on-Chip Routers. Neural Net-works. 2012 Sep; 33:42–57. Crossref PMid:22561008
- Indiveri G, Linares-Barranco B, Hamilton TJ, Schaik VA, et al. Neuromorphic Silicon Neuron Circuits. Frontiers in Neuroscience. 2011 Jan; 5:73. Crossref PMid:21747754 PMCid:PMC3130465
- Strogatz SH. Exploring Complex Networks. Nature. 2001 mar; 410(6825):268–76. Crossref PMid:11258382
- Watts DJ, Strogatz SH. Collective Dynamics of ‘SmallWorld’ Networks. Nature. 1998 Jun; 393(6684):440–2. Crossref PMid:9623998
- Bassett DS, Greenfield DL, Meyer-Lindenberg A, Weinberger DR, Smoore W, Bullmore ET. Efficient Physical Embedding of Topologically Complex Information Processing Networks in Brains an Computer Circuits. PLoS Computational Biology. 2010 Apr; 6(4):e1000748. Crossref PMid:20421990 PMCid:PMC2858671
- Markram H. The Blue Brain Project. Nature Rev. Neuroscience. 2006; 7(2):153–9. Crossref PMid:16429124
- Blumrich M, Chen D, Coteus P, Gara A, Giampapa M. Design and Analysis of the Bluegene/L Torus Interconnection Network. IBM Research Report RC23025 (W0312-022),2003; 23025.
- Schemmel J, Fieres J, Meier K. Wafer-Scale Integration of Analog Neural Networks. Proc. IEEE Int’l Joint Conf. Neural Networks. 2008 Jun; 431–8. Crossref
- Bruderle D, Petrovici MA, Vogginger B, Ehrlich M, et al. A Comprehensive Workflow for General-Purpose Neural Modeling with Highly Configurable Neuromorphic Hardware Systems. Biological Cybernetics. 2011 May; 104(4/5):263–96. Crossref PMid:21618053
- Carrillo S, Harkin J, McDaid LJ, Morgan F, Pande S, Cawley S, McGinley B. Scalable Hierarchical Network-onChip Architecture for Spiking Neural Network Hardware Implementations. IEEE Transactions on Parallel And Distributed Systems. 2013 Dec; 24(12). Crossref
- Diehl PU, Pedroni B, Cassidy A, Merolla P, Neftci E, Zarrella G. Truehappiness: Sentiment analysis on truenorth. arXiv, 2016.
- Cao Y, Chen Y, Khosla D. Spiking deep convolutional neural networks for energy-efficient object recognition. International Journal of Computer Vision. 2014; 1–13
- D. Neil, Liu S-C. Minitaur, an event-driven fpga-based spiking network accelerator. IEEE Transactions on Very Large Scale Integration (VLSI) Systems.2014; 22(12):2621– 8. Crossref
- Stromatias E, Neil D, Pfeiffer M, Galluppi F, Furber SB, Liu S-C. Robustness of spiking deep belief networks to noise and reduced bit precision of neuro-inspired hardware platforms. Frontiers in neuroscience, 2015; 9. Crossref
- Esser SK, Appuswamy R, Merolla P, Arthur JV, Modha DS. Backpropagation for energy-efficient neuromorphic computing. Advances in Neural Information Processing Systems. 2015; 1117–25.
- Li X, Roth D. Learning question classifiers. Proceedings of the 19th international conference on Computational linguistics. 2002; 1:1–7. Crossref
- Mikolov T, Chen K, Corrado G, Dean J. Efficient estimation of word representations in vector space. arXiv preprint arXiv:1301.3781, 2013.
- Levy O, Goldberg Y. Neural word embedding as implicit matrix factorization. Advances in Neural Information Processing Systems. 2014; 2177–85.
- Li Y, Xu L, Tian F, Jiang L, Zhong X, Chen E. Word embedding revisited: A new representation learning and explicit matrix factorization perspective. 2015.  Schmidhuber J. Deep learning in neural networks: An overview. Neural Networks. 2015; 61:85–117.
- Merolla PA, Arthur JV, Alvarez-Icaza R, Cassidy AS, et al. A million spiking-neuron integrated circuit with a scalable communication network and interface. Science. 2014; 345(6197):668–73. Crossref PMid:25104385
- Indiveri G, Chicca E, Douglas R. A VLSI array of low-power spiking neurons and bistable synapses with spike–timing dependent plasticity. IEEE Transactions on Neural Networks. 2006 Jan; 17(1):211–21. Available from: Crossref Crossref PMid:16526488
- Khan M, Lester D, Plana L, Rast A, Jin X, Painkras E, Furber S. Spinnaker: mapping neural networks onto a massively parallel chip multiprocessor. IEEE International Joint Conference on Neural Networks, IJCNN, 2008. IEEE, p. 2849–56. Crossref
- Benjamin BV, Gao P, McQuinn E, Choudhary S, et al. Neurogrid A mixed-analog-digital multichip system for large-scale neural simulations. Proceedings of the IEEE. 2014; 102(5):699–716. Crossref
- LeCun Y, Bottou L, Bengio Y, Haffner P. Gradient-based learning applied to document recognition. Proceedings of the IEEE. 1998; 86(11):2278–324. Crossref
- There are currently no refbacks.
This work is licensed under a Creative Commons Attribution 3.0 License.