Total views : 179

Reconfigurable Low Pass FIR Filter Design using Canonic Signed Digit for Audio Applications


  • National Institute of Techincal Teachers Training and Research, Chandigarh –160019, India


Objectives: This paper highlights the design of multiplier-less FIR filter. The binary coefficients are replaced by Canonic Signed Digit representation which reduces the complexity of the design. Methods/Statistical Analysis: In the current scenario more research is going on the optimization of Finite Impulse Response filters with less complex hardware design. The FIR filters performance depends on number of coefficient multipliers. The multipliers are expensive in terms delay area and power. In the CSD based filter, the number of non-zero bits is reduced. This proposed filter is designed in MATLAB, simulated in ISE environment and implemented on FPGA. Findings: The proposed filter is implemented on three FPGA devices, Xilinx's Spartan-3E, xc3s500e-4fg320, Virtex 2P, 2vp30ff1152-5 and Virtex 5P xc5v1x50t-3ff1136. Improvements: The designed structure uses reduced number of hardware components like slices, look up tables (LUTs) and flip-flops as compared to different structures and offers better performance.



Full Text:

 |  (PDF views: 106)


  • Priya K, Mehra R. Area efficient design of FIR filter using symmetric structure. International Journal of Advanced Research in Computer and Communication Engineering. 2012 Dec;, 1(10): 842–5.
  • Goel N, Nandi A. Design of FIR filter using FCSD representation. InComputational Intelligence & Communication Technology (CICT),.2015 IEEE International Conference. 2015 Feb.p.617–20. Crossref
  • Mehra R, Devi S. Area efficient and cost effective pulse shaping filter for software radios. International Journal of Ad hoc Sensor and Ubiquitous Computing (IJASUC).2010 Sep; 1: 85–91.
  • Mehra R, Kaur R. Reconfigurable area and speed efficient interpolator using DALUT algorithm. InInternational Conference on Computer Science and Information Technology, 2011 Jan.p.117–25. Crossref
  • Mohanty BK, Meher PK. A high-performance FIR filter architecture for fixed and reconfigurable applications. IEEE transactions on very large scale integration (vlsi) systems. 2016 Feb; 24(2): 444–-52.
  • Priya K, Mehra R. FPGA based cost efficient FIR filter using Factored CSD technique.IJRTE. 2013 Jan; 1(6): 1–4.
  • Mahesh R, Vinod AP. New reconfigurable architectures for implementing FIR filters with low complexity.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2010 Feb; 29(2): 275–88. Crossref
  • Vaidyanathan P, Nguyen T. Eigenfilters. A new approach to least-squares FIR filter design and applications including Nyquist filters. IEEE Transactions on Circuits and Systems. 1987 Jan; 34(1): 11–23. Crossref
  • Vishwanath BR, Theerthesha TS. Multiplier using canonical signed digit code. International Journal for Research in Applied Science & Engineering Technology (IJRASET). 2015; 3(5): 415–20.
  • Rajolia A, Kaur M. Finite Impulse Response (FIR) filter design using Canonical Signed Digits (CSD). IJSR India Online. 2013; 2 (7): 1–3.
  • Kolawole ES, Ali WH, Cofie P, Fuller J, Tolliver C, Obiomon P. Design and implementation of Low-Pass HighPass and Band-Pass Finite Impulse Response (FIR) filters using FPGA. Circuits and Systems. 2015 Feb; 6(2): 30–48. Crossref
  • Kamble P, Deote N, Wanjari N, Gaikwad S. Implementation of FIR filter structure for audio application using XilinxSystem generator. International Journal of Advanced Research in Computer Science and Software Engineering. 2015; 5(1): 762–5.
  • Mehra R, Saini G, Singh S. FPGA based high speed BCH encoder for wireless communication applications. In Communication Systems and Network Technologies (CSNT) International Conference..2011 Jun.p.576–9. Crossref


  • There are currently no refbacks.

Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.