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FPGA Based Equiripple Canonical Signed Digit FIR Filter for Audio Applications


  • National Institute of Techincal Teachers Training and Research, Chandigarh – 160019, India


Objective: In this work, the selection of equiripple optimum design approach along with Canonical Signed Digital (CSD) representation of filter coefficients give an efficient and simplified design for Finite Impulse Response (FIR) digital filter. Methods/Statistical Analysis: The modern sophisticated communication devices demand for digital filters having the best possible performance. In this paper the author introduces design of FPGA based CSD finite impulse response filter with the help of an equiripple design method which provides the best possible frequency response. The direct form structure adopted in realizing this filter has better performance in terms of cost, power consumption and speed of operation. Findings: The CSD representation of filter coefficients reduces the complexity of multipliers. The resource utilization of designed FIR CSD filter analyzes with the help of a number of performance parameters and compares with FIR fully parallel filter. The proposed filter uses MATLAB fdatool to determine filter coefficients and Xilinx ISE 9.2i to simulate the performance of filter. Applications: The proposed filter can be used in several audio applications.



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  • Thapaswini PP, Umadevi S, Sreerangaswamy V. Design and Optimization of Digital FIR Filter Coefficients using Genetic Algorithm. International Journal of Engineering and Technical Research. 2015; 3: 248–53.
  • Ruiz GA, Granda M. Efficient canonic signed digit recoding. Microelectronics Journal. 2011 Sep 30; 42(9):1090–7. Crossref
  • Priya K, Mehra R. FPGA based cost efficient FIR filter using Factored CSD technique.International Journal of Recent Trends in Electricla and Electronics Engineering (IJRTE). 2013 Jan; 1(6): 1–4.
  • kamble P, Deote N, Wanjari N, Gaikwad S. Implementation of FIR Filter Structure for audio applications using Xilinx system Generator. International Journal of Advanced Research in Computer Science and Software Engineering. 2015; 5(1): 762–5.
  • Goel N, Nandi A. Design of Optimized FIR Filter Using FCSD Representation. International Journal of Electrical and Electronics Engineering. 2015; 2 (1): 3–6.
  • Mehra R, Devi S. Area efficient and cost effective pulse shaping filter for software radios. International Journal of Ad hoc, Sensor and Ubiquitous Computing (IJASUC). 2010 Sep; 1(3): 85–91 Crossref
  • Mehra R, Kaur R. Reconfigurable Area and Speed Efficient Interpolator Using DALUT Algorithm. International Conference on Computer Science and Information Technology. 2011 Jan; 117–25. Crossref
  • Priya K, Mehra R. Area Efficient Design of FIR filter using symmetric structure. International Journal of Advanced Research in Computer and communication engineering. 2012 Dec; 1(10): 842–5.
  • Mohanty BK, Meher PK. A high-performance FIR filter architecture for fixed and reconfigurable applications. IEEE transactions on very large scale integration (vlsi) systems. 2016 Feb; 24(2): 444–52.
  • Kolawole ES, Ali WH, Cofie P, Fuller J, Tolliver C, Obiomon P. Design and Implementation of Low-Pass High-Pass and Band-Pass Finite Impulse Response (FIR) Filters Using FPGA. Circuits and Systems. 2015 Feb; 6 (2): 30–48. Crossref


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