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BCD Adder Design using New Reversible Logic for Low Power Applications

Affiliations

  • Department of Electrical Communication Engineering, SCETW, Affiliated to Osmania University, Hyderabad – 50000, Telangana, India

Abstract


Objectives: Proposed a novel GDI (Gate Diffusion Input) based low power BCD adder to improve the performance further compared with existing BCD adder design using BBCDC reversible gates. Methods/Analysis: Reversible logic is one of the potential techniques observed for low power designs having lot of research scope in the fields of nanotechnology, which involves with quantum computing. One major advantage of reversible logic is its low power capability. The power dissipation, speed, circuit density are the main concerns of research today. The proposed GDI cell based BBCDC reversible logic is implemented using Microwind 2, with 120nm technology. Findings: The proposed GDI based BBCDC reversible adder is proved that there is 91.5% of reduction in delay, 80.7% of reduction in power dissipation, 64.58% of reduction in logic overhead, and 93.88% of reduction in area when compared with the CMOS logic. The design goal is to minimize PDP, in order to get low power with high-speed advantage. Novelty /Improvement: The proposed GDI based BCD adder using reversible logic results in 98.38% of PDP advantage over existing designs, hence more reliable with extended performance.

Keywords

Area, BCD Adder, CMOS Logic, Figure of Merit, GDI Technology, Reversible Logic

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