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BCD Adder Design using New Reversible Logic for Low Power Applications


  • Department of Electrical Communication Engineering, SCETW, Affiliated to Osmania University, Hyderabad – 50000, Telangana, India


Objectives: Proposed a novel GDI (Gate Diffusion Input) based low power BCD adder to improve the performance further compared with existing BCD adder design using BBCDC reversible gates. Methods/Analysis: Reversible logic is one of the potential techniques observed for low power designs having lot of research scope in the fields of nanotechnology, which involves with quantum computing. One major advantage of reversible logic is its low power capability. The power dissipation, speed, circuit density are the main concerns of research today. The proposed GDI cell based BBCDC reversible logic is implemented using Microwind 2, with 120nm technology. Findings: The proposed GDI based BBCDC reversible adder is proved that there is 91.5% of reduction in delay, 80.7% of reduction in power dissipation, 64.58% of reduction in logic overhead, and 93.88% of reduction in area when compared with the CMOS logic. The design goal is to minimize PDP, in order to get low power with high-speed advantage. Novelty /Improvement: The proposed GDI based BCD adder using reversible logic results in 98.38% of PDP advantage over existing designs, hence more reliable with extended performance.


Area, BCD Adder, CMOS Logic, Figure of Merit, GDI Technology, Reversible Logic

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  • Sayem ASM, Ueda M. Optimization of reversible Sequential Circuits. Journal of Computing. 2010 Jun; 2(6):208–14.
  • Bennett CH. Logical Reversibility of Computation. IBM Journal of Research and Development; 1973 Nov. p. 525– 32. Crossref
  • Landauer R. Irreversibility and Heat Generation in the computational Process. IBM Journal of Research and Development. 1961 Jul; 5(3):183–91. Crossref
  • Kanth BR, Krishna BM, Sridhar M, Swaroop VGS. A distinguish between reversible and conventional logic gates. International Journal of Engineering Research and Applications. 2012 Mar-Apr; 2(2):148–51.
  • Mamataj S, Das S, Rahaman A. An Approach for Realization of 2s Complement Adder Substractor using DKG reversible gate. International Journal of Emerging Technology and Advanced Engineering. 2013 Dec; 3(12):205–9.
  • Babu HMH, Islam MR, Chowdhury AR, Chowdhury SMA. Synthesis of full-adder circuit using reversible logic17th International Conference on VLSI Design; 2004. p. 757–60.
  • Biswas AK, Hasan M, Hasan M, Chowdhury AR, Md H, Babu H. A Novel Approach to Design BCD Adder and Carry Skip BCD Adder. 21st International Conference on VLSI Design; 2008. p. 566–71.
  • Thapliyal H, Ranganathan N. Design of reversible sequential circuits optimizing quantum cost delay and garbage outputs. ACM Journal of Emerging Technologies in Computing Systems. ACM. New York, USA. 2010 Dec; 6(4).
  • Mamataj S, Das B, Rahaman A. A More Effective Realization of BCD Adder by using a new Technique Reversible logic BBCDC. International Journal of Computational Engineering Research. 2015 Feb; 4(2):13–9.
  • Suria ST, Jenath M. Design and Implementation of CLA Using reversible Logic Gates. International Journal of Innovative Research in Science Engineering and Technology. 2016 May; 5(5):2347–6710.
  • Smoline J, David P, Vincenzo D. Five Two-bit quantum gates are sufficient to implement the Quantum Fredkin Gate.1996; 53(4):2855–6.
  • Thapliyal H, Ranganathan N. A new reversible Design of BCD Adder; 2011. p. 1–4.
  • R. Feynman. Quantum Mechanical Computers Optical News. 1986; 16(6):11–20.
  • Fredkin E, Toffoli T. Conservative Logic International Journal of Theoretical Physics. 1982 Apr; 21(3):219–53. Crossref
  • Morgenshtein A, Fish A, Wagner IA. Gate-Diffusion Input (GDI) A Power-Efficient Method for Digital Combinatorial Circuits. IEEE Transactions on Very Large Scale Integration (VLSI) systems. 2002 Oct; 10(5):566–81.
  • Bhagyalakshmi HR,Venkatesh MK. Optimized reversible BCD adder using new reversible logic Gates. Journal of Computing. 2010 Feb; 2(2).
  • James RK, Shahana TK, Jacob KP, Sasi S. A New Look at Reversible Logic Implementation of Decimal Adder. System on-Chip. The International Symposium on System-onChip. Tampere, Finland; 2007. p. 1–4. Crossref PMCid:PMC1828102


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