Total views : 865
RNM Calculation of 6T SRAM Cell in 32nm Process Node based on Current and Voltage Information
Objectives: This work aims to analyze the the dependency of VDD, T and CR (Cell Ratio) on cell stability in terms of Read Noise Margin (RNM) in 32nm technology by the N- curve and butterfly graphical methods. The advantages of considering both voltage and current information for SRAM cell stability measurement have been reported. Methods/Statistical Analysis: The cell stability calculation of SRAM is a central concern in submicron CMOS process nodes, as they reason for increase in dies variability and voltage scaling. The cell Stability of the SRAM is typically calculated by Static Noise Margin (SNM). As it varies with different operating modes of a cell, a detailed analysis is required. In this article, the RNM of SRAM cell is computed by N curve, which compares with the SNM by bufferfly method. SRAM with PMOS access transistor for improved read stability and low voltage application is also presented. Findings: Results show that proposed SRAM gives 50% cell stability in read mode of operation over conventional SRAM cell for CR=3. Application/Improvements: The typical SRAM bit cell with PMOS access transistor shows improved read stability at low voltage application than standard SRAM cell.
Butterfly Curve, Cell Ratio, N-Curve, Pull-Up Ratio, Read stability, RNM, SNM, SRAM, Write Stability
- Chang YJ, Lai F, Yang CL. Zero-Aware Asymmetric SRAM Cell for Reducing Cache Power in Writing Zero. IEEE Transactions on Very Large Scale Integration Systems.2004; 12(8):827–36. Crossref
- Gupta S, Chowdhury AR, Roy K. Digital computation in subthreshold for ultralow-power operation: A device-circuitarchitecture code design perspective. Proceedings of the IEEE. 2010; 98(2):160–90. Crossref
- ITRS website. [Online]. Available from: http://www.itrs2.net/2011-itrs.html
- Pasandi G, Fakhraie SM. A 256-kb 9T Near-Threshold SRAM with 1K cells per Bit-Lines and enhanced Write and Read operations. IEEE Transactions on VLSI systems. 2015; 99:1–9.
- Pasandi G, Fakhraie SM. A new subthreshold 7T SRAM cell design with capability of bit-interleaving in 90nm CMOS, Proceedings of 21st Iranian Conference on Electrical Engineering (ICEE); 2013. p. 1–6.
- Seevinck E, List FJ, Lohstroh J. Static- Noise Margin Analysis of MOS SRAM cells. IEEE Journal of Solid-State Circuits. 1987; 22(5):748–54. Crossref
- Yamauchi H. A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2010; 18(5):763–74. Crossref
- Predictive Technology Model. [online]. Available From: http;//www.ptm.asu.edu Date Accessed: 2006.
- Changhwan S, Cho MH, Tsukamoto Y, Nguyen BY, Mazure C, Nikolic B, Liu TJK. Performance and Area Scaling Benefits of FD-SOI Technology for 6T SRAM Cells at the 22nm Node. IEEE Transactions on Electron Devices. 2010; 57(6):1301–9. Crossref
- Bhavnagarwala AJ, Kosonocky S, Radens C, Chan Y, Stawiasz K, Srinivasan U, Kowalczyk SP, Ziegler MM. Asub-600mV fluctuation tolerant 65nm CMOS SRAM array with dynamic cell biasing. IEEE Journal of Solid-State Circuit. 2008; 43(4):946–55. Crossref
- Lohstroh J. Static and Dynamic Noise Margins of Logic Circuits. IEEE Journal Solid-State Circuits. 1979; 14(3):591–8. Crossref
- Takeda K, Hagihara Y, Aimoto Y, Nomura M, Nakazawa Y, Ishii T, Kobatake H. A Read-Static-Noise-Margin-Free SRAM cell for low- VDD and High-speed applications.IEEE Journal of Solid-State Circuits. 2006; 41(1):113–21.Crossref
- Achankunju PL. Sreekala KS, James MK. Design and Read Stability Analysis of 8T Schmitt trigger based SRAM.ICTACT Journal of Microelectronics. 2017; 2(4):323–8.Crossref
- Wann C, Wong R, Frank DJ, Mann R, Ko SB, Croce P, Lea D, Hoyniak D, Lee YM, Toomey J, Weybright M, Sudijono J. SRAM cell design for stability methodology. Proc IEEE VLSI-TSA International Symposium; 2005. p. 21–2.Crossref
- Grossar E, Stucchi M, Maex K, Dehaene W. Read Stability and Write-Ability analysis of SRAM cells for nanometer Technologies. IEEE Journal of Solid-State Circuits. 2006; 41(11):2577–88. Crossref
- Saeidi R, Sharifkhani M, Hajsadeghi K. A Subthreshold Symmetic SRAM cell with High Read Stability. IEEE Transactions on Circuits and Systems-II: Express Beliefs.2014; 61(1).
- Rabaey JM, Chandrakasan A, Nikolic B. Digital Integrated Circuits: A design Perspective. 2nd edition. Prentice-Hall: New Delhi, India; 2002.
- Saha SK. Compact MOSFET modeling for Process Variability-Aware VLSI circuit design. IEEE Access. 2014; 2:104–15. Crossref
- Guo Z, Pang LT, Duong KT, Liu TJK, Nikolic B. Large-scale SRAM variability characterization in 45nm CMOS. IEEE J. Solid-State Circuits. 2009; 44(11):3174–92. Crossref
- Toh SO, Guo Z, Liu TJK, Nikolic B. Characterization of dynamic SRAM stability in 45nm CMOS. IEEE J. SolidState-Circuits. 2011; 46(1):2702–12. Crossref
- There are currently no refbacks.
This work is licensed under a Creative Commons Attribution 3.0 License.