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RNM Calculation of 6T SRAM Cell in 32nm Process Node based on Current and Voltage Information

Affiliations

  • Department of Electronics, School of Technology and Applied Sciences, Mahatma Gandhi University, Edappally, Kochi – 682024, Kerala, India

Abstract


Objectives: This work aims to analyze the the dependency of VDD, T and CR (Cell Ratio) on cell stability in terms of Read Noise Margin (RNM) in 32nm technology by the N- curve and butterfly graphical methods. The advantages of considering both voltage and current information for SRAM cell stability measurement have been reported. Methods/Statistical Analysis: The cell stability calculation of SRAM is a central concern in submicron CMOS process nodes, as they reason for increase in dies variability and voltage scaling. The cell Stability of the SRAM is typically calculated by Static Noise Margin (SNM). As it varies with different operating modes of a cell, a detailed analysis is required. In this article, the RNM of SRAM cell is computed by N curve, which compares with the SNM by bufferfly method. SRAM with PMOS access transistor for improved read stability and low voltage application is also presented. Findings: Results show that proposed SRAM gives 50% cell stability in read mode of operation over conventional SRAM cell for CR=3. Application/Improvements: The typical SRAM bit cell with PMOS access transistor shows improved read stability at low voltage application than standard SRAM cell.

Keywords

Butterfly Curve, Cell Ratio, N-Curve, Pull-Up Ratio, Read stability, RNM, SNM, SRAM, Write Stability

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