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Performance Analysis of Emerging Interconnects Driven by Devices beyond CMOS
Objective: This paper analyses the performances of Multi Walled Carbon Nanotube (MWCNT), Mixed CNT Bundle (MCB), and Multilayer Graphene Nanoribbon (MLGNR) interconnects incorporated with Carbon Nanotube Field-Effect Transistor (CNFET) and Tunnel Field-Effect Transistor (TFET) technologies. Methods/Statistical Analysis: The performances of the circuits are evaluated at the 32-nm node. HSPICE is used for the simulation of the driver interconnect load framework. The performance parameters, viz. power dissipation, propagation delay, and power delay product (PDP), are assessed, and it is found that a CNFET driver can reduce the propagation delay in MLGNR interconnects by 96%, 38%, and 30%, for local, intermediate, and global interconnect lengths, respectively, in comparison with the TFET driver. Findings: By using a TFET driver, the power dissipation in MLGNR is reduced by 99%, 45%, and 63%, for local, intermediate, and global levels, respectively, compared to the CNFET driver. The PDP of MLGNR is reduced by 99%, 37%, and 47% for local, intermediate, and global levels, respectively, by using a TFET driver instead of a CNFET driver. Applications/Improvements: MLGNR shows lesser propagation delay, power dissipation, and PDP than the MWCNT and MCB interconnects; hence, it is considered the best candidate to replace Cu interconnects in Very-Large-Scale Integration (VLSI) chips.
Copper, Driver Interconnect Load. Integrated Circuits, Mixed CNT Bundle, Multilevel Graphene Nano Ribbon, Multiwalled Carbon Nanotubes, Power Delay Product, Tunnel Field Effect Transistor, Very-Large-Scale-Integration
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