Total views : 617
Low Power Techniques for Digital System Design
The proliferation of reconfigurable hardware like (FPGAs) put a challenge in front of designers to implement fast and low powered digital designs. Main drawbacks of FPGAs are the complex circuitry which makes them less efficient as compared to ASIC (Application Specific Integrated Circuits). Although appropriate to scaling in CMOS technology reduce the power required for performing the known job, it increase clout indulgence for each part of region. At similar instant request of low power application is swelling due to increase of smart devices and increasing energy costs. Since power consumption is an extremely significant issue in digital classification of designs, so the authors have presented and analyzed some power reduction techniques that can be targeted at different levels of design hierarchy for different target platform. The authors would also discuss concept of ACPI module designed for newer operating systems, which provides basic power management facilities to save system power.
ACPI, Clock Tree, Flattening and Factorization, Low Uncertainty Clock Tree (LUCT)
- Mishra S, Verma G. Low power and area efficient implementation of BCD Adder on FPGA. International Conference on Signal Processing and Communication (ICSC’2013); Noida: JIIT; 2013 Dec 12–14. p. 461–5.
- Zhao P. Design of sequential elements for low power clocking system. IEEE Transactions of VLSI Systems. 2009; 19(5):914–8.
- Vijeyakumar KN, et al. FPGA implementation of low power hardware efficient flagged binary coded decimal adder. International Journal of Computer Application. 2012 May; 46(14):41–5.
- Al-Khaleel OD, et al. FPGA implementation of binary coded decimal digit adders and multipliers. 8th International Symposium on Mechatronics and its Applications (ISMA); 2012 Apr 10–12. p. 1–4.
- Pawel PC, Andrzej S. Power optimization techniques in FPGA devices: A combination of system- and low-levels. World Academy of Science, Engineering and Technology International Journal of Computer, Information Science and Engineering. 2007; 1(4):148–54. Available from: http://www.waset.org/Publication/8418
- Anderson JH, Najm FN. A novel low-power FPGA routing switch. IEEE Proceedings of the Custom Integrated Circuits Conference; 2004 Oct 3–6. p. 719–22.
- Lamoureux J, Luk W. An overview of low-power techniques for field-programmable gate arrays. NASA/ESA ConferenceAdaptive Hardware and Systems (AHS’08); Noordwijk. 2008. p. 338–45.
- Sabri MFM, Othman IN, Husin MH. Development of 5-bit, 4-Inputs PWM generator on FPGA through VHDL Programming. International Conference on Advance Science and Contemporary Engineering (ICASCE’2012); 2012. p. 486–93.
- Bishwajeet P, et al. Clock gating based energy efficient ALU design and implementation on FPGA. IEEE International Conference on Energy Efficient Technologies for Sustainability (ICEETs); Nagercoil, Tamil Nadu. 2013 Apr 10–12. p. 93–7.
- Chen D, et al. Low-power high-level synthesis for FPGA architecture. Proceedings of the 2003 International Symposium on Low Power Electronics and Design (ISLPED’03); 2003 Aug 25–27. p. 134–9.
- Chen D, et al. Optimal module and voltage assignment for low-power. Proceedings of Asia South Pacific Design Automation Conference; 2005 Jan 18–21. p. 850–5.
- Derek C. Power Consumption in 65 nm FPGAs. Xilinx; 2007 Feb 1; 1(2):1–12.
- Subodh G, Jason A. Optimizing FPGA power with ISE design tools. Xcell Journal. 2007 Jun 4; (60):16–9.
- Roy K. Power-dissipation driven FPGA place and route under timing constraints. IEEE Transaction on Circuits and Systems. 1999 May; 46(5):634–7.
- There are currently no refbacks.
This work is licensed under a Creative Commons Attribution 3.0 License.