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Reversible SSG Gate for Implementing Parity Checker Generator and Magnitude Comparator


  • Electronics and Communication Engineering department, SRM University, Chennai - 603203, Tamil Nadu, India


The objective is to design a new reversible logic gate for implementing parity checker and generator logic circuit and a magnitude comparator logic circuit with minimum computational time. Power dissipation seems to be a major drawback in all conventional irreversible logic circuits. As a solution to this, circuits can be constructed using reversible logic gates. According to the principle of reversible logic a new 3X3 gate named as SSG gate has been proposed. SSG gate has the ability to realize the following logic functions like XOR, NOR, OR, NOT, XNOR, AND and COPY. The proposed work can be implemented on a floating point subtractor and multiplier design. The proposed SSG gate is used to test the functionality of a even parity checker and generator circuit and it is compared with the circuit realized using existing Feynman gate. The comparative result shows that SSG parity checker and generator consumes 0.67 seconds less time compared with the existing gate. The comparative result of the 2-bit magnitude comparator designed using proposed SSG gate and with the existing reversible gate1 and Gate2 shows that the computation time for SSG gate comparator is reduced by 0.33 seconds with the existing reversible gate1 and gate2.


Magnitude Comparator, Parity Checker, Parity Generator, Reversible Logic.

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