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Pipelined Architecture for Motion Estimation in HEVC Video Coding


  • School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, India


Background: High Efficiency Video Coding (HEVC) is the latest video coding standard for video coding. Motion estimation is one of important stages in video coding. In HEVC, the conventional macroblocks are replaced by coding tree units (CTU). Method/Statistical Analysis: The maximum block size is increased from 16×16 to 64×64 in HEVC makes motion estimation more complex. An efficient hardware architecture ha to be designed for real time implementation of motion estimation. In motion estimation, sum of absolute difference (SAD) is calculated between current block and reference blocks present in two different video frames and minimum of SAD gives motion vector of the block. Findings: This paper presents design of pipelined SAD architecture for efficient SAD calculations. The proposed design is used in diamond search algorithm to carry out the motion estimation for evaluating the performance of the design. The proposed architecture employs pipelining at 8×8 block. The proposed design is implemented in TSMC 90 nm technology and operates at maximum frequency of 486 MHz. Applications/Improvements: The design achieves 78% reduction in power compared to the previous design and around 50 % increase in operating frequency.


H.264/AVC, H.265/HEVC, Motion Estimation, Motion Vector, Sum of Absolute Difference.

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