Total views : 305

Built in Self Test Architecture using Concurrent Approach

Affiliations

  • School of Electronics Engineering, VIT University, Chennai-600127, Tamil Nadu, India

Abstract


Background/objectives: Built in Self Test Architectures are used for the online or offline testing of the digital circuits and can be operated both in normal as well as test mode. So the objective is to test the circuit under test in online mode with less concurrent test latency and less area overhead. Methods/ Statistical Analysis: In the case of normal mode the time required for testing becomes undesirable parameter so here we prefer offline testing method with concurrent approach which is also monitoring the window at the input by applying input vectors considering circuit under test as most important part of the processor which is arithmetic logic unit. Findings: The particular locations of the input vectors are stored in the latches which worked as the memory elements and this proposed scheme becomes more efficient by using cellular automata as test pattern generation and response analyzer using rule 90. Application/Improvement: The proposed scheme is comparable with the same architecture, considering TPG as LFSR (Linear Feedback Shift Register) and counter.

Keywords

Arithmatic Logic Unit, Built in Self Test, Cellular Automata, Concurrent Test Latency, LFSR, Memory Elements, TPG, Windowing.

Full Text:

 |  (PDF views: 371)

References


  • Voyiatzis I, Efstathiou C.Input vector monitoring concurrent BIST architecture using SRAM cells. IEEE Transactions on VLSI Systems. 2014; 22(7):1625-29.
  • Akshay D, Sharma SM, Vyas LA, Sivasankaran K.Design of low power and area efficient 4-bit arithmetic and logic unit using nanoscaleFinFET. Indian Journal of Science and Technology. 2015 Jan; 8(S2):1–7. DOI: 10.17485/ijst/2015/v8iS2/70759.
  • Begum JT, Naidu HS, Vaishnavi N, Sakana G, PrabhakaranN. Design and Implementation of Reconfigurable ALU for Signal Processing Applications. Indian Journal of Science and Technology. 2016 Jan; 9(2):1–6. DOI: 10.17485/ijst/2016/v9i2/86343.
  • Nandal A, Vigneswaran T, Rana AT. Booth multiplier using reversible logic with low power and reduced logical complexity. Indian Journal of Science and Technology. 2014 Jan; 7(4):525–29. DOI: 10.17485/ijst/2014/v7i4/48644.
  • Athithan S, Shukla VP, Biradar SR. Voting rule based cellular automata epidemic spread model for leptospirosis. Indian Journal of Science and Technology. 2015 Feb; 8(4):337–41. DOI: 10.17485/ijst/2015/v8i4/60441.
  • Voyiatzis I, Paschalis A, Gizopoulos D, Kranitis N, Halatsis C. A concurrent BIST architecture based on a selftesting RAM.IEEE Transactions on Reliability.2005; 54(1):69–78.
  • Kochte MA, Zoellin C, Wunderlich HJ. Concurrent self-test with partially specified patterns for low test latency and overhead.2009 14th IEEE European Test Symposium; 2009 May. p. 53–58.
  • Saluja KK, Sharma R, Kime CR. A concurrent testing technique for digital circuits.IEEE Transactions on Computer-Aided Design of Integrated Circuits Systems. 1988; 7(12):1250–26.
  • Sharma R,Saluja KK. Theory, analysis and implementation of an on-line BIST technique. VLSI Design.1993; 1(1):9–22.
  • Zorian Y, Ivanov A. An effective BIST scheme for ROM’s.IEEE Transactions on Computers. 1992; 41(5):646–53.
  • Voyiatzis I, Haniotakis T, Efstathiou C, Antonopoulou H. A concurrent BIST architecture based on monitoring square windows.2010 5th International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), Hammamet; 2010 Mar. p. 1–6.
  • Kochte MA, Zoellin C, Wunderlich HJ. Concurrent self-test with partially specified patterns for low test latency and overhead. in Proc. 14th Eur. Test Symp.,Seville,2009, pp. 53–58.
  • A. Kumaravel, Meetei ON. An application of non-uniform cellular automata for efficient cryptography. Indian Journal of Science and Technology,2013 May, 6(S5), pp. 1-7. DOI: 10.17485/ijst/2013/v6i5S/33355.
  • Kamaraj A, Marichamy P, Devi SK, Subraja MN. Design and implementation of adders using novel reversible gates in quantum cellular automata. Indian Journal of Science and Technology. 2016 Feb; 9(8):1–7. DOI: 10.17485/ijst/2016/v9i8/87929.
  • Sinha N,Ravi V. Implementation of health monitoring system using mixed environment. Indian Journal of Science and Technology. 2015 Aug; 8(20):1–7. DOI:10.17485/ijst/2015/v8i20/77727.
  • Pandharpurkar NG, Ravi V. Design of BIST using self-checking circuits for multipliers. Indian Journal of Science and Technology. 2015 Aug; 8(19):1–7. DOI: 10.17485/ijst/2015/v8i19/77006.

Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.