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Implementation of Low Power Pipelined 64-bit RISC Processor with Unbiased FPU on CPLD

Affiliations

  • Department of Physics, SKUCET, Sri Krishnadevaraya University, Anantapur - 515003, Andhra Pradesh, India
  • Department of Applied Sciences, St. Ann’s College of Engineering Technology, Chirala - 523187, Andhra Pradesh, India
  • Department of Physics, Government Arts and Science College, Anantapur - 515 001, Andhra Pradesh, India
  • Department of Physics, Sri Krishnadevaraya University, Anantapur - 515003, Andhra Pradesh, India

Abstract


Background/Objective: Now a day’s electronics industry people are concentrating on low power designs. The growing market of portable electronic systems demands microelectronic circuit with ultra low power dissipation. Method: The accomplished operations in this design are logical operations, the arithmetic operations, and branch operations. The outcome values of these operations stored in the registers and they can retrieve from the same when needed. The low power RISC processor with unbiased double precision FPU is designed without any complication, because the power reduction can do in front end technique. Findings: On MAX V CPLD a low power pipelined 64-bit RISC processor is implemented. Arithmetic operations, logical and branch functions of RISC processor are successfully verified with this design. In order to avoid any misbehavior in the jump instructions, the data will flush in the pipeline automatically by the processor architecture. This processor contains FPU unit, which supports double precision IEEE-754 format operations very accurately. Modelsim software is used to verify the simulation results of the design. The ALU operations and double precision floating point arithmetic operation results will be displayed on 7-Segments.

Keywords

Altera Max V, CPLD, Low power, Modelsim, RISC.

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