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Various Techniques to Overcome Noise in Dynamic CMOS Logic
The advent of dynamic logic especially domino logic has made the use of dynamic circuits very wide for the implementation of low power VLSI circuits. Dynamic logic style is becoming the designers' choice these days because it has very fast speed and occupies very small area. In this paper we have used various techniques based on domino logic to overcome noise. Each technique has its merits and demerits. Out of these techniques mentioned below we have taken two widely used techniques in domino logic, conditional keeper technique and diode footed domino. We calculated their noise margins at different values of supply voltage. We have done simulations in 90 nm technology. After calculations we found both techniques show fairly good noise immunity but diode footed domino gave better results.
Delay, Diode Footed Domino, Immunity, Leakage Tolerance, Noise, Power Consumption, Subthreshold Voltage, Technology Scaling.
- Ding, Mazumder P. On circuit techniques to improve noise immunity of CMOS dynamic logic. IEEE TransactionsonVery Large Scale Integration VLSI Systems. 2004 Sep; 12(9).
- Govindarajulu S, Prasad TJ, Sreelakshmi C, Chandrakala, Thirumalesh U. Energy efficient, noise tolerant CMOS domino VLSI circuits in VDSM technology. IJACSA. 2011; 2(4).
- Mahmoodi H, Roy K. Diode footed domino: A leakage tolerant high fan in dynamic circuit design style. IEEE Transactions Circuits and Systems. 2004 Mar; 51(3)495–503.
- Booba S, Hajj IN. Design of dynamic circuits with enhanced noise tolerance. Proceedings of 12th Annual IEEE International ASIC/SOC Conference; Washington, DC. 1999 Feb. p. 54–8.
- Wang L, Krishnamoorthy R, Soumyanath K, Shanbhag N. An energy efficient leakage tolerant dynamic circuit technique. Proceedings of International ASIC/SOC conference; 2000 Apr. p. 221–5.
- Kursun V. Domino logic with variable threshold voltage keeper. IEEE Transactions. 2003 Dec; 11(6).
- Assaderaghi F, et al. Dynamic threshold voltage MOSFET for ultra low voltage VLSI. IEEE Trans Electron Devices. 1997 Mar; 44:414–22.
- Pattanaik M, Parashar S, et al. A novel low noise tolerant high performance dynamic feed through logic design technique. International Symposium on Electronics System Design; 2011 Oct.
- Anis MH, Allam MW, Elmarsy MI. Energy-efficient noise tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies. IEEE Trans Very Large Scale Integr Syst. 2002 Sep; 10(2):71–8.
- Wang L, Shanbhag NR. An energy efficient noise tolerant dynamic circuit technique. IEEE Transactions Circuits and Systems-II: Analog and Digital Signal Processing. 2000 Nov; 47(11).
- Govindarajulu S, Jayachandra T, et al. Energy efficient, noise-tolerant CMOS domino VLSI circuits in VDSM Technology. International Journal of Advanced Computer Science and Applications. 2011; 2(4).
- Alvandpour A, Krishnamurthy R, Sourrty K, Borkar SY. A sub-130-nm conditional-keeper technique. IEEE J Solid-State Circuits. 2002 May; 37(5):633–8.
- Jung S-O, Kim KW. Noise constraint transistor sizing and power optimization for dual V T domino logic. IEEE Transactions on VLSI Systems. 2002 Oct; 10(5).
- Peiri A, Asyaei M. Current-comparison-based domino: New low-leakage high-speed domino circuit for wide fan-in gates. IEEE Trans Very Large Scale Integration (VLSI) Systems. 2013 May; 21(5).
- De V, Borkar S. Technology and design challenges for low power and high performance. Proc Int Symp Low Power Electronics and Design, ISLPED 99; San Diego, CA, USA. 1999 Aug. p. 163–38.
- Kim J, Roy K. A leakage tolerant high fan-in dynamic circuit design technique. Proc 27th European Solid-State Circ Conf, ESSCIRC; Villach, Austria. 2001 Sep. p. 309–12.
- Ye Y, Borkar S, De V. A new technique for standby leakage reduction in high-performance circuits. Proc IEEE Symp on VLSI Circuits. 1998. p. 40–1.
- Choi SH, Somasekhar D, Roy K. Dynamic noise model and its application to high-speed circuit design. Microelectron J. 2002; 33:835–46.
- Stan MR, Panigrahi A. The Selective Pull-up (SP) noise immunity scheme for dynamic circuits. Proc Design, Automation and Test in Europe 2002; Paris, France. 2002 Mar. p. 1106.
- Sinthuja S, Kumar JH, Manoharan N. Energy efficient voltage conversion range of multiple level shifter design in multi voltage domain. Indian Journal of Science and Technology. 2014; 7(6):82–6.
- Sanapala K, Sakthivel R. Low power realization of subthreshold digital logic circuits using body bias technique. Indian Journal of Science and Technology. 2016; 9(5):1–5.
- Karthikeyan A, Arunarasi J, Arul Mary A. a neoteric fpga architecture with memristor based interconnects for efficient power consumption. Indian Journal of Science and Technology. 2016; 9(5):1–9.
- Hemalatha SB, Vigneshwaran T, Jasmin M. survey on energy-efficient methodologies and architectures of network-on-chip. Indian Journal of Science and Technology. 2016; 9(2):1–8.
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