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FPGA Implementation and Analysis of the Block Cipher Mode Architectures for the PRESENT Light Weight Encryption Algorithm

Affiliations

  • School of Electronics Engineering, VIT University Chennai, Chennai - 600127, India

Abstract


Objective: This paper presents the Field Programmable Gate Array (FPGA) implementations of the different block cipher mode architectures of the ISO standardized light weight block cipher PRESENT, designed for resource constrained devices. Methods/ Statistical Analysis: The performance evaluations compare the implementations of the different block cipher modes, namely Electronic Code Book (ECB) mode, Cipher Block Chaining (CBC) mode, Cipher Feedback Mode (CFB), Output Feed Back Mode (OFB) and CounTeR (CTR) mode for the PRESENT cipher. The throughput of encryption of three successive 64 bit blocks of data ranges from 565.312Mbps to 574.784Mbps for the modes other than the cipher feedback mode in the Spartan-3 FPGA. The throughput for providing confidentiality through encryption in the cipher feedback mode arrives as 68.912 Mbps, 155.392Mbps and 300.8 Mbps for a 64 bit block of data for the input streams of size 8 bits, 16 bits and 32 bits respectively. Findings: The throughput of the block cipher mode hardware architectures of the light weight cipher PRESENT demonstrates the high speed performance of the cipher in encryption/decryption of data as blocks and streams. Application/ Improvement: The significance of the proposed work is to know the hardware performance of the different modes of operation for the light weight block cipher PRESENT. The performance estimation of the block cipher modes operations of the PRESENT cipher definition in hardware have been carried out for the first time.

Keywords

Block Cipher Modes, FPGA, Internet of Things (IoT), Light Weight Cipher.

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