Total views : 304
Low Power and High Speed PB-CAM with XNOR-NAND Parameter Comparison Circuit
Objectives: Low power consumption, high-speed and low-cost are the major important needs in several applications like Asynchronous Transfer Mode (ATM) and Giga-bit Ethernet networks. To achieve high-speed parallel data comparisons in internet routers PB-CAM is the one of best hardware approaches. In the present work, PB-CAM is modified for improving performance of CAM architecture. Methods/Statistical Analysis: In PB-CAM unit the main building blocks of the process is parameter extractor, parameter comparison circuit and CAM cell. The PB-CAM is faster and low-power consumption than the traditional CAM. The PB-CAM unit implemented by 180nm, 90nm and 45nm CMOS technology in Cadence. The parameter-extractor and static-parameter-comparison circuits implemented in 180nm, 90nm and 45nm CMOS technology. Findings: The power consumption of the proposed Parameter-Comparison circuit using XNOR-NAND CMOS logic is 0.02135uW at a supply voltage of 0.45V in 45nm CMOS technology for a 4x4 (4-bits of stored parameter-extracted data and 4-bits of input parameter-extracted data) size parameter comparison data at 10-30MHz. For 15-bit input data, the PB-CAM with proposed parameter comparison circuit is consuming an average power of 129.1uW at a supply of 0.9V and a frequency of 10-30MHz. The results show that the PB-CAM unit using proposed parameter comparison circuit is faster, low-power consumption and low-cost than the PB-CAM with static parameter comparison circuit. Application/Improvements: PB-CAM circuit used in high-speed look-up-tables (LUTs), ATMs, routers and etc. In future, further advancements can be done in PB-CAM unit by combining different techniques such as match-line-sense-amplifier, ones-count, block-XOR, parity-bit to achieve low-power, low-cost and high-speed search and read operations in network routers.
ATM, Cadence, CAM, Ethernet, High-Speed, Low-Cost, Low Power, Match-Line, PB-CAM, Routers.
- Lin CS, Chang JC, Liu BD. A low-power pre-computation based fully parallel content-addressable memory. IEEE J Solid-State Circuits. 2003; 38(4):622–54.
- Tanenbaum AS. Computer Networks, Prentice Hall, Upper Saddle River, NJ, 2003.
- Kobayashi M, Murase T, Kuriyama A. A longest prefix match search engine for multi-gigabit IP processing. Proceedings of the IEEE International Conference on Communications, Japan. 2000; 3. p. 1360–4.
- Mohan N. Low-power high-performance ternary content addressable memory circuits, Ph.D. thesis, Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, Canada. 2006; 1–156.
- Ruan SJ, Wu CY, Hsieh JY. Low Power Design of Precomputation-Based Content-Addressable Memory. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2008; 16(3):331–5.
- Wade JP, Sodini CG. A ternary content-addressable search engine. IEEE J Solid-State Circuits. 1989; 24(4):1003–13.
- Pagiamtzis K, Sheikholeslami A. Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey. IEEE Journal of Solid-State Circuits. 2006; 41(3):712–27.
- Kang SM, Leblebici Y. CMOS Digital Integrated Circuits Analysis and Design, Third Edition, McGraw Hill Education, India. 2013.
- Zackriya VM, Verma A, Harish M, Kittur K. Design of Multi-Segment Hybrid Type Content Addressable Memory in High Performance FinFET Technologies. Indian Journal of Science and Technology. 2015; 8(24):1–6.
- Pai YT, Lee CH, Ruan SJ, Naroska E. An Improved Comparison Circuit for Low Power Pre-computation-Based Content-Addressable Memory designs© Germany, 2009.
- Liu SC, Wu FA, Kuo JB. A novel low-voltage content-addressable- memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques. IEEE J Solid-State Circuits. 2001; 36(1):712–6.
- Miyatake H, Tanaka M, Mori M. A design for high-speed low power CMOS fully parallel content-addressable memory macros. IEEE J Solid-State Circuits. 2001; 36:956–68.
- Kim JK, Vlasenko P, Perry D, Gillingham PB. Low power content addressable memory architecture, US Patent 6584003. 2003.
- Cheng KH, Wei CH, Chen YW. Design of Low-Power Content-Addressable Memory cell. IEEE 46th Midwest Symposium on Circuits and Systems, Taiwan. 2003; 3:1447–50.
- Chang YJ, Wu TC. Master–Slave Match Line design for low-power content-addressable memory. IEEE transactions on very large scale integration (vlsi) systems. 2015; 23(9):1740–9.
- Do AT, Chen S, Kong ZH, Yeo KS. A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013; 21(1):151–6.
This work is licensed under a Creative Commons Attribution 3.0 License.