Total views : 277

A New Approach for Low Power Decoder for Memory Array


  • School of Computing, SASTRA University, Thanjavur - 613401, Tamil Nadu, India


SRAMs are important building blocks in many digital applications, such as microprocessors and cache memories. Decoders are the significant components in SRAMs. Address decoder is vital part of SRAM memory. Choice of capacity cell and read operation is relies on upon decoder. Henceforth, execution of SRAM is relies on upon these parts. This work studies the location decoder for SRAM memory, focusing on deferral streamlining and control effective circuit systems. We have focused on ideal decoder structure with slightest number of transistors to diminish range of SRAM. Usually, in Memory Chip, it consumes almost fifty percent of the total chip access time and power. Parameters which has to be considered while designing an address decoders are, first appropriate circuit technique has to be chosen and the second thing is sizing constrains of the transistors. Modified hybrid type of decoding topology is illustrated and it is compared with traditional type decoders which include both static and dynamic types using 180 nm CMOS technology in Cadence Virtuoso environment.


Buffer Control, Cadence and Power Consumption, SRAM, Static Decoder.

Full Text:

 |  (PDF views: 277)


  • Turi MA, Delgado-Frias JG. Reducing power in memory decode by means of selective precharge schemes. IEEE Journal. 2007 50th Midwest Symposium on Circuits and Systems; Monteal. 2007 Aug 5-8. p. 956–9.
  • Ashwin JS, Praveen JS, Manoharan N. Optimization of SRAM array structure for energy efficiency improvement in advanced CMOS Technology. Indian Journal of Science and Technology. 2014; 7(S6):35–9.
  • Akashe S, Sinha DK, Sharma S. A low-leakage current power 45 nm CMOS SRAM. Indian Journal of Science and Technology. 2011; 4(4):440–2.
  • Kang SM, Leblebigi Y. CMOS digital IC circuit design and analysis. McGraw Hill; 2003.
  • Amrutur BS, Horowitz MA. Fast low-power decoders for RAMs. IEEE Journal of Solid-State Circuits. 2001Oct; 36(10):1506–15.
  • Turi M, Frias J. High-performance low-power selective pre-charge schemes for address decoder. IEEE Trans on Circuits and Systems. 2008 Sep; 55(9):917–21.
  • Brzozowski I, Zachara L, Kos A. Universal design method of n-to-2n decoders. Mixed Design of Integrated Circuits and Systems Conference; Poland. 2013 Jun. p. 279–84.


  • There are currently no refbacks.

Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.