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Cell Stability and Power Reduction using Dynamic Isolated Read Static Random Access Memory


  • School of Computing, SASTRA University, Thanjavur -613401, Tamil Nadu, India


The channel scaling attains the overflow current at the transistor, which impacts on power indulgence. In order to attain reduced power and delay, the devices are assumed to decrease its size. Then transistors size can also be changed. In this paper the unique dynamic isolated read SRAM has been projected for dropping the total power. By linking, the cell with 6T and NC SRAM in numerous features, high constancy and decreased power is achieved by the curvature N (noise) method, which is done when the system is in active mode. The values are calculated with the voltage of 1.8 which reduces 90% of power than the 6T, and 18% of power is reduced than the 8T SRAM cell, and 30% of leakage current is reduced as compared to 6T cell. Thus when related to the existing SRAM, the cell consumes less power and without any distortion the cell stores the data. Also the constancy of the cell is improved when compared with the other cell. The waveform result shows that the cell attains enhanced stability and reduction in overflow using the cadence virtuoso technology of 180 nm.


Curvature-noise, Stability, Static Current Noise Margin, Static Voltage Noise Margin, Write Trip Point.

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