Total views : 263

Digital Infinite Impulse Response Filter with Floating Point Multiply Accumulate Circuit using Pipelining

Affiliations

  • PG Scholar, School of Computing, SASTRA University, Thanjavur – 613401, Tamil Nadu, India

Abstract


A competent architecture for IIR filter is designed. It is configured and folded, which will be used in the real time applications like loud speaker and equalization of digital signal processing. A basic feature of digital signal processing is filtering. Filtering is a choosy system which passes an assured choice of frequency and attenuating the others frequency. Digital filtering is a prevailing sector of DSP allied works. A system of digital filter performs mathematical operations on a sampled or discrete time variant signal to contract or improve certain aspects of that signal. The configurable folded IIR filter for sixth order is designed using three series of second order IIR filter. This IIR filter architecture is used to carry out three second order or a one sixth order. It can be also used to execute one fourth order and one second order in parallel according to the requirement where, each second order IIR filter is designed using multiply accumulate circuit which as floating point. Here pipelining of IIR filter for second order is proposed to increase the throughput by reducing the critical path delay. The proposed sixth order IIR filter using three second order IIR filter with pipelining achieves 39.7% of increased throughput and it operates at high frequency of 85.068MHz compared with conventional MAC based architecture.

Keywords

IIR Filter, Multiply Accumulate Circuit (MAC), Pipeline.

Full Text:

 |  (PDF views: 229)

References


  • Xiao F. Fast design of IIR digital filters with a general Chebyshev characteristic. IEEE Transactions on Circuits and Systems-II: Express Briefs. 2014 Dec; 61(12):962–6.
  • McGovern BP, Woods RF, McAllister C. Optimised multiply/ accumulate architecture for very high throughput rate digital filters. IET Electronic Letters. 1995 Jul; 31(14):1135–6.
  • Xu C, Wang C-Y, Parhi KK. Order-configurable programmable power-efficient FIR filters. IEEE International Conference on High Performance Computing; 1996 Dec. p. 357–61.
  • Basiri MMA, Mahammad SKN. An efficient hardware based MAC design in digital filters with complex numbers. IEEE International Conference on Signal Processing and Integrated Networks (SPIN); 2014 Feb. p. 475–80.
  • Yazhini M, Ramesh R. FIR Filter implementation using modified distributed arithmetic architecture. Indian Journal of Science and Technology. 2013 May; 6(5):1–7.
  • Kumar CU, Rabi BJ. Design and implementation of modified Russian peasant multiplier using MSQRTCSLA based Fir filter. Indian Journal of Science and Technology. 2016 Feb; 9(7):1–6. DOI: 10.17485/ijst/2016/v9i7/82311.
  • Basiri MA, Mahammad SKN. An efficient hardware based higher radix floating point MAC design. ACM Transactions On Design Automation of Electronic Systems (TODAES). 2014 Nov; 20(1).

Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.