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A VLSI Architecture of Root Raised Cosine Filter Using Efficient Algorithm
This paper describe about a reduction of area and power using Vertical and Horizontal Common Sub-Expression Elimination Algorithm in root raised cosine filter. The common sub-expression elimination algorithm is commonly used to reduce the number of adders present the given multiplier architecture is done by reducing MPIS (Multiplications per Input Samples) and APIS (Additions per Input Samples). In the 2bit and 3-bit BCSE algorithms, shift and add method was proposed. Those provide less area than the normal multiplier. Hence algorithm is proposed to further reduce the area utilization, power consumption .Area is utilized by reducing the number of gates in the architecture. This algorithm used for implementing higher adder filters with very few adders and few stages. The proposed algorithm is used to multiply both the signed and unsigned constant multiplication. Here the adjacent co-efficient are grouped by 2bit, 4bit and 8bit grouping as per the horizontal and vertical common sub-expressions. The Shift and add method is used to reduce the number of adders. Similarly multiplexers are used for switching activity to reduce the adders and multiplication stages. These operations are applied to the RRC FIR filter with the different standards. The whole work is done in Quartus II 9.2 web edition, cyclone III
2-bit BCSE, CSE, RRC Filter, VHBCSE Algorithm.
- Joost M. Theory of root-raised cosine filter [Internet]. 2010 Dec. Available from: http://www.michael-joost.de/rrcfilter.pdf.
- Mitola J. The software radio architecture. IEEE Communications Magazine. 1995 May; 3(5):26–38.
- Yu YJ, Lim YC. Optimization of linear phase FIR filters in dynamically expanding sub-expression space. Circuits Systems Signal Process. 2010 Feb; 29(1):65–80.
- Vinod AP, Lai EMK. An efficient coefficient-partitioning algorithm for realizing low complexity digital filters. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2005 Dec; 24(12):1936–46.
- Mahesh R, Vinod AP. New reconﬁgurable architectures for implementing FIR ﬁlters with low complexity. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2010 Feb; 29(2):275–88.
- Durairajaa N, Joyprincy J, Palanisamy M. Design of low power and area efficient architecture for reconfigurable FIR filter. International Journal of Recent Technology and Engineering. 2013 Mar; 2(1):1–6.
- Hsiao SF, Jian JHZ, Chen MC. Low-cost FIR filter designs based on faithfully rounded truncated multiple constant multiplication/accumulation. IEEE Transactions on Circuits and Systems—II: Express Briefs. 2013 May; 60(5):287–91.
- Deepika A, Bhuvaneswari A. Low power FIR filter design using truncated multiplier. International Journal of Engineering Trends and Technology. 2014 Apr; 10(1):1–6.
- Lee SJ, Choi JW, Kim SW, Park J. A reconﬁgurable FIR ﬁlter architecture to trade off ﬁlter performance for dynamic power consumption. IEEE Transactions Very Large Scale Integration. (VLSI) Systems. 2011 Dec; 19(12):2221–8.
- Pillai R, Beulet PAS. Design and implementation of low-power, area-efficient FIR filter using different distributed arithmetic techniques. Indian Journal of Science and Technology. 2015 Sep; 8(21):1–5. DOI: 10.17485/ijst/2015/v8i21/79128.
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