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High Throughput Pipelining NoC using Clumsy Flow Control


  • School of Computing, SASTRA University, Thirumalaisamudram, Thanjavur - 613401, Tamil Nadu, India
  • School of Computing, Information Technology, SASTRA University, Thanjavur - 613401, Tamil Nadu, India


Network on-Chip (NoC) is a novel technology which is used to make the interconnections between the components available in the System on Chip (SoC) design. This technology of NoC is defined and used in two varied forms as buffered and bufferless NoC. Bufferless NoC, a predominant type of network on chip, is used to reduce the cost efficiently by removing input buffers of the router. However, it is evident that this performance gets jammed at high loads because of the increase in the network contentions and deflection of packets in huge amount. To reduce the amount of deflection and to buttress the flow, Clumsy Flow Control (CFC) is used in the bufferless NoC. In this paper, a novel proposal has been propounded into the pipelining mechanism keeping in mind the flawless flow control needed for the bufferless NoC to decrease the impact of deflection routing and to increase the throughput with high injection rate. Employing the pipelining technique into the existing flow control increases the frequency which in turn, is responsible for high throughput. Implementation of the aforementioned pipelining mechanism is done in two stages in the bufferless NoC which helps to increase the throughput as well as the injection rate. Finally, the application with its pipelined implementation, as proposed, will be mapped onto the NoC architecture by using the CFC.


Bufferless NoC, CFC, Network on Chip, Pipeline, Router.

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  • Dally WJ, Towles B. Principles and Practices of Interconnection Networks. San Francisco, CA: Morgan Kaufmann; 2004 Jan.
  • Moscibroda T, Mutlu T. A case for bufferless routing in onchip networks. ISCA. 2009 Jun; 196–207.
  • Hayenga M, Lipasti M, Enright JN. SCARAB: A single cycle adaptive routing and bufferless network. 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO); 2009 Dec. p. 244–54.
  • Kim H, Kim Y, Kim J. Clumsy flow control for highthroughput bufferless on-chip networks. IEEE Computer Architecture Letters. 2013 Jul–Dec; 12(2):47–50.
  • Rantala V, Lehtonen T, Plossila J. Network on Chip routing algorithms. TUCS Technical Report No. 779. Turku Center for Computer Science; 2006 Aug. p. 1-38 .
  • Fallin C. CHIPPER: A low-complexity bufferless deflection router. IEEE 17th International Symposium on High Performance Computer Architecture; 2011 Feb. p. 144-55.
  • Stojanovic IZ, Jovanovic MD, Djordjevic GLJ. Low-cost port allocation scheme for minimizing deflections in bufferless on-chip networks. 21st International conference on Telecommunications Forum; 2013 Nov. p. 357-60.
  • Kang YH, Kwon TJ, Draper J. Fault-tolerant flow control in on-chip networks. IEEE 4th International Conference on Networks-on-Chip; 2010. p. 79-86.
  • Talebi MS, Jafari F, Khonsari A. A novel flow control scheme for best effort traffic in NoC based on source rate utility maximization. Modeling Analysis and Simulation of Computer and Telecommunication Systems. 2007 Oct; 381–6.
  • Mullins R, West A, Moore S. The design and implementation of a low-latency on-chip network. Asia and South Pacific Conference on Design Automation; 2006 Jan.
  • Tang M, Lin X. Injection level flow control for networkonchip. Journal of Information Science and Engineering.2011; 27:527-44.
  • Selvaraj G, Kashwan KR. Reconfigurable adaptive routing buffer design for scalable power efficient network on chip. Indian Journal of Science and Technology. 2015 Jun; 8(12):1-9.
  • Beulah HS, Vigneshwaran T, Jasmin M. Survey on energy-efficient methodologies and architectures of Network-on-Chip. Indian Journal of Science and Technology. 2016 Mar; 9(12):1-8.


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