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Low Power Testing based on MOS Design Modified Flip-Flop

Affiliations

  • School of Computing, SASTRA University, Thanjavur – 613401, Tamilnadu, India

Abstract


Flip-flops are basically data storage elements which can be used for storage of state. However, most non-volatile memory forms have limitations which make them unsuitable for primary storage. One of the disadvantages of existing flip-flop normal flip-flop based circuits and its computing is relatively high write energy to build up normal flip-flop based circuits. There is a need to reduce the consumption of power and to write energy of flip-flop. Hence, we propose a design of low power normal flip-flop using modified CMOS technology. CMOS technology provides less noise ration during design. The proposed flip-flop design is based on MOS technology. Data store and restore operations can be performed. And in the proposed design performs in retaining data when electrical power fails or is turned off with low power consumption.

Keywords

CMOS Design, D Flip-Flop, Low Power.

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References


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