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Low Latency Noc with Dynamic Priority based Matrix Arbiter

Affiliations

  • School of Computing, SASTRA University, Thanjavur - 613401, Tamil Nadu, India

Abstract


The quest for the improvement of processing power and efficiency is spawning research for many core systems. Network on chip (Noc) is evolving as an eminent way in replacing shared buses for better design and reusability. The packet switch fabric posses a high dominant problem which gives rise to high latency and communication uncertainty. Packet requirements can be detected and dispatched from different directions based on the priorities so that the packets pass through the router in a congestion free manner. Network on chip replaces the shared bus system and routing is performed in a multi hop basis. Router architectures have been proposed to reduce the average network delay. However communication uncertainty becomes more critical to system performance. Pipelining stage can further increase the throughput as much as possible. A priority arbitration technique is used in this paper to reduce the average latency by Dynamic priority based matrix arbiter in the pipelining stage. If many packets want to get access to the same output channel, the role of router is to decide which packet should be delivered to the next router. The scheduling algorithm is implemented with the matrix arbitration technique in the pipelining stage which increases the speed of communication. With the help of the tool Xilinx ISE 14.2 the parameters of throughput and latency is analyzed.

Keywords

Arbitration, Dynamic Priority (DP), Matrix arbiter, Network on chip (Noc), Pipelining.

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References


  • Benini L, Micheli GD. Networks on chips: A new SoC paradigm. Computer. 2002 Jan; 35(1):70–8.
  • Beulah HS, Vigneshwaran T, Jasmin M. Survey on energy - Efficient methodologies and architectures of Network-onChip. Indian Journal of Science and Technology. 2016 Mar; 9(12):1-8.
  • Mullins R, West A, Moore S. Low-latency virtual-channel routers for on-chip networks. 31st Annual International Symposium on Computer Architecture (ISCA); p. 1-10.
  • Selvaraj G, Kashwan KR. Reconfigurable adaptive routing buffer design for scalable power efficient Network on Chip. Indian Journal of Science and Technology. 2015 Jun; 8(12):1-9.
  • Howard J, Dighe S, Vangal SR. A 48-core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling. IEEE J Solid-State Circuit. 2011 Jan; 46(1):173–83.
  • Yan K, Yang H. A Low Latency Variance NoC Router and Hui Wang Institute of Circuits and Systems. Dordrecht: Springer Science+Business Media; 2012. p. 89-97.
  • Matsutani H, Koibuchi M, Amano H. Prediction router: Yet another low latency on-chip router architecture. IEEE 15th International Symposium on High Performance Computer Architecture (HPCA); 2009 Feb. p. 367–78.
  • Park D, Das R, Nicopoulos C. Design of dynamic prioritybased fast path architecture for on-chip interconnects. 15th Annual IEEE Symposium on High-Performance Interconnects; 2007 Aug. p. 15–20.
  • Daneshtalab M, Pedram A, Neishaburi MH, Riazat M, Afzalikusha A, Mohammadi S. Distributing congestions in Noc through a dynamic routing algorithm based on input and output selections. Proceedings of International Conference on VLSI Design; 2007 Jan. p. 546-50.
  • Dally WJ. Virtual-channel flow control. 17th Annual International Symposium on Computer Architecture (ISCA); 1990 May. p. 60–8.
  • Chan C-H, Tsai K-L, Lai F, Tsai S-H. A priority based output arbiter for NoC router. IEEE International Symposium of Circuits and Systems (ISCAS); 2011 May. p. 1928–31.
  • Kim J, Nicopoulos C. A gracefully degrading and energyefficient modular router architecture for on-chip networks. Proceedings of the 33rd International Symposium on Computer Architecture (ISCA’06); 2006 May. p. 4–15.
  • Fu Z, Ling X. The design and implementation of arbiters for Network-on-chips. International Conference on Industrial and Information Systems; National Key Laboratory of Science and Technology on Communications of UESTC; 2010 Jul. p. 292–5.

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