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Design of Out-of-Order Floating-Point Unit

Affiliations

  • Department of ECE, SRM University, Chennai-603203, Tamil Nadu, India

Abstract


Objective: Field Programmable Gate Arrays (FPGAs) are often used to accelerate hardware systems by implementing algorithms on hardware. This paper presents the design and implementation of a fully pipelined single-precision Floating-Point Unit (FPU) on a Spartan-6 FPGA chip. Methods: This paper presents a high-speed, modular design for improving the performance of such applications. While the proposed design is capable of performing basic arithmetic operations and square-root extraction, its modularity enables designers to add more functionality easily; or remove modules that they deem unnecessary for a particular application. Findings: The investigation shows that the adder and multiplier modules can be clocked at over 300 MHz and the top-module at over 200 MHz High operating frequencies were achieved by pre-computing possible values in earlier pipelining stages, then correcting results in later pipelining stages. It was also found that splitting longer operations in the critical path is a better alternative than processing the whole operation at once. Limiting “Max_Fanout”, an attribute provided by Xilinx XST tool, proved valuable in reducing delays on overloaded nets. Applications: This FPU would be a worthwhile addition as a floating-point extension in fixed-point processors for applications such as spectrum analyzers, 3D graphics, and audio processing units.

Keywords

DSP48A1Multiplier, FPU, FPGA, High-speed Pipeline, Out-of-order Processing, Non-restoring Algorithm, Spartan-6, Single-Precision

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