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Low Power High Speed based Various Adder Architectures using SPST


  • School of Computing, Sastra University, Thanjavur - 613401, Tamil Nadu, India
  • Department of Electrical Engineering, JEC, Jabalpur - 482011, Madhya Pradesh, India


Adder is a circuit that is combinational andcalculates the sum of three (full adder) or two (half adder) inputs. Full adder can be cascaded to produce n-stages of adder. This cascaded adder structure is called as parallel adder. The sum and carry outputs of any stage cannot be calculated until the input carry occurs, this leads to a delay in the addition process. In order to overcome the delay, carry look ahead adder is proposed which is said to be a fast adder. To improve the speed of vary look ahead adder, Spurious Power Suppression Technique (SPST) is used. This paper discusses 8-bit adder consisting of three architectures parallel adder, normal carry look ahead adder and SPST carry look ahead adder. The results were simulated using Xilinx tools and as shown, the power has decreased for both the SPST carry look ahead adder and the SPST ripple carry adder. The code was written in Verilog HDL and tested on a Xilinx FPGA test board as a part of a velocity measurement circuit for an Electromagnetic Projectile Launcher.


Adder, Full Adder, Power, Parallel Adder, SPST.

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